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CHAPTER 18
Figure 18-22. Example of Communication from Master to Slave (with 9-Clock Wait Selected for Both
Master and Slave) (3/3)
Processing in master device
SIO0 <- data
SIO0 write
COI
ACKD
CMDD
RELD
L
CLD
P27
H
L
WUP
L
BSYE
L
ACKE
CMDT
RELT
CLC
L
WREL
L
SIC
INTCSI0
Transfer line
SCL
D7
SDA0
Processing in slave device
SIO0 write
COI
ACKD
CMDD
RELD
CLD
P27
WUP
BSYE
H
ACKE
H
L
CMDT
RELT
L
CLC
L
WREL
H
SIC
INTCSI0
CSIE0
P25
PM25
L
PM27
SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries)
(c) Stop condition
1
2 3 4 5 6 7 8
9
D6
D5 D4 D3 D2 D1 D0 ACK
SIO0 <- FFH
SIO0 <- address
SIO0 <- FFH
1 2 3 4
A6 A5 A4 A3
403
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