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CHAPTER 18
(a) Start condition
When the SDA0 (SDA1) pin level is changed from high to low while the SCL pin is high, this transition is
recognized as the start condition signal. This start condition signal, which is created using the SCL and
SDA0 (or SDA1) pins, is output from the master device to slave devices to initiate a serial transfer.
Refer to 18.4.5 Cautions on use of I
The start condition signal is detected by hardware incorporated in slave devices.
(b) Address
The 7 bits following the start condition signal are defined as an address.
The 7-bit address data is output by the master device to specify a specific slave from among those
connected to the bus line. Each slave device on the bus line must therefore have a different address.
Therefore, after a slave device detects the start condition, it compares the 7-bit address data received
and the data of the slave address register (SVA). After the comparison, only the slave device in which
the data are a match becomes the communication partner, and subsequently performs communication
with the master device until the master device sends a start condition or stop condition signal.
SCL
SDA0 (SDA1)
(c) Transfer direction specification
The 1 bit that follows the 7-bit address data will be sent from the master device, and it is defined as the
transfer direction specification bit. If this bit is 0, it is the master device which will send data to the slave.
If it is 1, it is the slave device which will send data to the master.
SCL
SDA0 (SDA1)
392
SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries)
2
C bus mode, for details of the start condition output.
Figure 18-15. Start Condition
H
SCL
SDA0 (SDA1)
Figure 18-16. Address
1
2
A6
Figure 18-17. Transfer Direction Specification
1
2
A6
3
4
5
6
A5
A4
A3
A2
Address
3
4
5
6
A5
A4
A3
A2
7
A1
A0
R/W
7
8
A1
A0
R/W
Transfer direction
specification
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