CHAPTER 23 EXTERNAL DEVICE EXPANSION FUNCTION
Figure 23-7. External Memory Write Timing in Multiplexed Bus Mode
ASTB
WR
AD0 to AD7
A8 to A15
ASTB
WR
AD0 to AD7
A8 to A15
Internal Wait Signal
(1-clock wait)
ASTB
WR
AD0 to AD7
A8 to A15
WAIT
(a) No wait (PW1, PW0 = 0, 0) setting
Hi-Z
Lower Address
Higher Address
(b) Wait (PW1, PW0 = 0, 1) setting
Hi-Z
Lower Address
(c) External wait (PW1, PW0 = 1, 1) setting
Hi-Z
Lower Address
Write Data
Write Data
Higher Address
Write Data
Higher Address
537