Cautions On Use Of I C Bus Mode; Start Condition Output - NEC PD78076 User Manual

Pd78078 series; pd78078y series 8-bit single-chip microcontrollers

Table of Contents

18.4.5 Cautions on use of I

(1) Start condition output (master)

The SCL pin normally outputs a low-level signal when no serial clock is output. It is necessary to change the SCL

pin to high in order to output a start condition signal. Set the bit 3 (CLC) of the interrupt timing specify register

(SINT) to drive the SCL pin high.

After setting CLC, clear CLC to 0 and return the SCL pin to low. If CLC remains 1, no serial clock is output.

If it is the master device which outputs the start condition and stop condition signals, confirm that CLD is set

to 1 after setting CLC to 1; a slave device may have set SCL to low (wait state).

SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries)

Figure 18-24. Start Condition Output