Table of Contents
Advertisement
Instruction Mnemonic
Group
Conditional BT
saddr.bit, $addr16
branch
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
[HL].bit, $addr16
BF
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
[HL].bit, $addr16
BTCLR
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
[HL].bit, $addr16
DBNZ
B, $addr16
C, $addr16
saddr. $addr16
CPU
SEL
RBn
control
NOP
EI
DI
HALT
STOP
Notes 1. For instructions that access the internal high-speed RAM area or perform no data access
2. For instructions that access an area other than the internal high-speed RAM area
Remarks 1. One clock in the "Clock" columns is equal to one cycle of the CPU clock (f
clock control register (PCC).
2. The values in the "Clock" column assumes that the internal ROM area contains programs.
3. n indicates wait cycles to be inserted when an external expansion memory area is read from.
4. m indicates wait cycles to be inserted when an external expansion memory area is written to.
CHAPTER 28 INSTRUCTION SET
Operands
Byte
Clock
Note 1 Note 2
3
8
4
—
3
8
3
—
3
10
4
10
4
—
3
8
4
—
3
10
4
10
4
—
3
8
4
—
12+n+m PC
3
10
2
6
2
6
3
8
2
4
1
2
2
—
2
—
2
6
2
6
Operation
9
PC
PC + 3 + jdisp8 if(saddr.bit) = 1
11
PC
PC + 4 + jdisp8 if sfr.bit = 1
—
PC
PC + 3 + jdisp8 if A.bit = 1
9
PC
PC + 3 + jdisp8 if PSW.bit = 1
11 + n
PC
PC + 3 + jdisp8 if (HL).bit = 1
11
PC
PC + 4 + jdisp8 if(saddr.bit) = 0
11
PC
PC + 4 + jdisp8 if sfr.bit = 0
—
PC
PC + 3 + jdisp8 if A.bit = 0
11
PC
PC + 4 + jdisp8 if PSW. bit = 0
11 + n
PC
PC + 3 + jdisp8 if (HL).bit = 0
12
PC
PC + 4 + jdisp8 if(saddr.bit) = 1
then reset(saddr.bit)
12
PC
PC + 4 + jdisp8 if sfr.bit = 1
then reset sfr.bit
—
PC
PC + 3 + jdisp8 if A.bit = 1
then reset A.bit
PC + 4 + jdisp8 if PSW.bit = 1
then reset PSW.bit
12
PC
PC + 3 + jdisp8 if (HL).bit = 1
then reset (HL).bit
—
B
B – 1, then
PC
PC + 2 + jdisp8 if B
—
C
C –1, then
PC
PC + 2 + jdisp8 if C
10
(saddr)
(saddr) – 1, then
PC
PC + 3 + jdisp8 if(saddr)
—
RBS1, 0
n
—
No Operation
6
IE
1 (Enable Interrupt)
6
IE
0 (Disable Interrupt)
—
Set HALT Mode
—
Set STOP Mode
Flag
Z AC CY
x
x
x
0
0
0
) selected by the processor
CPU
591
Advertisement
Table of Contents
