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Figure 6-3. Interrupt Priority Specification Register
Address
3
2
FB2H
IPS3
IPS2
CHAPTER 6 INTERRUPT AND TEST FUNCTIONS
Symbol
1
0
IPS1
IPS0
IPS
High-order interrupt selection
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Interrupt master enable flag (IME)
All interrupts are disabled and no vectored interrupt is
0
activated.
The interrupt enable flag corresponding to an interrupt
1
request flag controls interrupt enabling/disabling.
0
All low-order interrupt
The listed vectored
VRQ1
1
interrupts are treated
(INTBT/INT4)
as high-order interrupts.
VRQ2
0
(INT0)
VRQ3
1
(INT1)
VRQ4
0
(INTCSI)
VRQ5
1
(INTT0)
VRQ6
0
(INTT1)
1
Not to be set
189
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