Emulation Memory Operation Timing Difference - NEC IE-703102-MC-EM1 User Manual

Pin Name
A0 to A23
D0 to D15
WE
OE
RD
ADV/BCYST
UWR/UCAS
LWR/LCAS
IORD
IOWR
CS0 to CS7
RAS0 to RAS7
REFRQ
WAIT
HLDRQ
HLDAK
Note Performs the same operation as the cycle that is generated by the target device program execution.

4.7 Emulation Memory Operation Timing Difference

When the area of the DRAM, synchronous flash memory, or page ROM in the target system has been allocated to
the emulation memory, the operation timing is the SRAM access timing.
When measuring the performance by using the emulation memory, adjust the setting so that the wait set matches
the memory access timing that is actually used.
CHAPTER 4
Table 4-2. Bus Interface Pin Operation List (3/3)
(c) Refresh cycle
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Maskable
Maskable
Note
CAUTIONS
Operation
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