Implementation - Xilinx Virtex-4 RocketIO User Manual

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Implementation

The MGT CRC blocks do not recognize start-of-frame (SOF/SOP) and end-of-frame
(EOF/EOP), nor do they decode CRC error conditions; this functionality must be
implemented in the FPGA fabric.
value for a packet using the CRC block.
Program
Attributes
Start of
Packet?
Strobe CRCINIT
Set the CRCDATAWIDTH
Assert CRCDATAVALID
Calculate New CRC
No
Packet?
Yes
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
No
Yes
Value
End of
Set CRCDATAWIDTH
to Remaining #
Bytes
Figure 5-6: CRC Generation Diagram
www.xilinx.com
Figure 5-6 shows a state machine that generates the CRC
CRCOUT[31:0]
Calculate New
CRC Value
Implementation
Invert CRCOUT[31:0]
to get CRC value
Deassert
CRCDATAVALID
ug076_ch5_07_102505
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