Figure 2-18: Resetting The Transmitter Where Tx Buffer Is Bypassed; Receive Reset Sequence: Rx Buffer Used - Xilinx Virtex-4 RocketIO User Manual

R
7.
Figure 2-18
bypassed. Refer to

Receive Reset Sequence: RX Buffer Used

Figure 2-19
Refer to the following points in conjunction with this figure:
•
•
•
•
•
•
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
TX_READY: TX link is ready.
TXPMARESET == 0
TXRESET == 0
TXSYNC == 0
shows a timing diagram for resetting the transmitter when the TX buffer is
Figure 2-16
TXUSRCLK
TXPMARESET
TXLOCK
TXSYNC
TXRESET

Figure 2-18: Resetting the Transmitter Where TX Buffer Is Bypassed

provides a flow chart of the receive reset sequence when the RX buffer is used.
The flow chart uses RXUSRCLK as reference to the wait time for each state. Do not use
RXUSRCLK as the clock source for this block; this clock might not be present during
some states. Use a free-running clock (for example, the system's clock) and make sure
that the wait time for each state equals the specified number of RXUSRCLK cycles.
It is assumed that the frequency of RXUSRCLK is slower than the frequency of
RXUSRCLK2. If RXUSRCLK2 is slower, use that clock as reference to the wait time for
each state.
rx_usrclk_stable is a status signal from the user's application that is asserted High
when both RXUSRCLK and RXUSRCLK2 clocks are stable. For example, if a DCM is
used to generate both the RXUSRCLK and RXUSRCLK2 clocks, then the DCM
LOCKED signal can be used here.
rx_error is a status signal from the user's application that is asserted High to indicate
that there is either an RX buffer error (RXBUFERR==1) or a burst of errors on the
received data (RXDISPERR and/or RXNOTINTABLE signals are asserted).
rx_pcs_reset_cnt is a counter from the user's application that is incremented every
time both the rx_error and RXLOCK signals are asserted. It is reset when the block
cycles back to the RX_PMA_RESET state.
See "RX Reset Sequence Background," page 100
cycles requirement.
www.xilinx.com
and Figure 2-17 for more details.
Once TX phase alignment error is monitored Low for some time, TX Link is READY
for information on the 16K REFCLK
Resets
ug076_ch2_19_040606
93