Implementation - Xilinx 7 Series User Manual

Chapter 1: Transceiver and Tool Overview

Implementation

Functional Description
This section provides the information needed to map 7 series GTP transceivers instantiated in a
design to device resources, including:
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It is a common practice to define the location of GTP transceiver Quads early in the design process
to ensure correct usage of clock resources and to facilitate signal integrity analysis during board
design. The implementation flow facilitates this practice through the use of location constraints in
the UCF.
This section describes how to instantiate GTP transceiver clocking components.
The position of each GTP transceiver channel and common primitive is specified by an XY
coordinate system that describes the column number and the relative position within that column.
For a given device/package combination, the transceiver with the coordinates X0Y0 is always
located at the lowest position of the lowest available bank.
There are two ways to create a UCF for designs that utilize the GTP transceiver. The preferred
method is to use the 7 Series FPGAs Transceivers Wizard. The Wizard automatically generates UCF
templates that configure the transceivers and contain placeholders for GTP transceiver placement
information. The UCFs generated by the Wizard can then be edited to customize operating
parameters and placement information for the application.
The second approach is to create the UCF by hand. When using this approach, the designer must
enter both configuration attributes that control transceiver operation as well as tile location
parameters. Care must be taken to ensure that all of the parameters needed to configure the GTP
transceiver are correctly entered.
If a design requires the use of any of the GTP channels in a given GTP Quad, a GTPE2_COMMON
primitive must be instantiated as shown in
GTPE2_CHANNEL must also be instantiated.
primitives instantiated.
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The location of the GTP transceiver Quads on the available device and package combinations.
The pad numbers of external signals associated with each GTP transceiver Quad.
How the GTPE2_CHANNEL primitive, the GTPE2_COMMON primitive, and clocking
resources instantiated in a design are mapped to available locations with a user constraints file
(UCF).
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Figure 1-5. At a minimum, at least one
Figure 1-5 shows four GTPE2_CHANNEL
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016