Synchronization Clock = Grefclk, Txphasesel = False - Xilinx Virtex-4 RocketIO User Manual

Chapter 8: Low-Latency Design
Skew
Note:
significant sources of skew within the FPGA. User must also account for skew on the board and at the
receiver end to determine the total skew seen at the receiver.

Synchronization Clock = GREFCLK, TXPHASESEL = FALSE

TXSkew
Skew
because the PMA-generated parallel clock (PMA TXCLK0) aligns from 0–2 UI ahead of the
parallel clock used as a timing reference (PCS TXCLK or GREFCLK).
Skew
(synchronization clock), 100 ps worst case.
Skew
USRCLK period for 1-byte and 2-byte fabric widths if the internal PCS dividers are used.
This is because the phase relationship of the internal PCS dividers is asynchronous
between MGTs. For 4-byte fabric width, there is no divider, so the skew is 0. For 2-byte and
1-byte mode, the skew in UI depends on the internal datapath used:
Skew
Note:
significant sources of skew within the FPGA. User must also account for skew on the board and at the
receiver end to determine the total skew seen at the receiver.
216
2-byte:
32-bit internal datapath: 16UI
40-bit internal datapath: 20UI
1-byte:
32-bit internal datapath: 24UI
40-bit internal datapath: 30UI
is the worst-case package skew between differential pairs, 70 ps.
Pkg
This skew calculation is accurate to the package pin at the TX side accounting for all
( )
UI = Skew
worstcase TXSYNC Algnmt
------------------------------------------- - UI
= 2UI +
UI
is the worst-case skew from the TXSYNC alignment circuit. This is 2 UI
TXSYNC Algnmt
is the worst-case clock skew across the FPGA for the alignment reference
ClkRef
is the skew from the internal USRCLK dividers. In the worst case, it is one
USRCLKDiv
2-byte:
32-bit internal datapath: 16UI
40-bit internal datapath: 20UI
1-byte:
32-bit internal datapath: 24UI
40-bit internal datapath: 30UI
is the worst-case package skew between differential pairs, 70 ps.
Pkg
This skew calculation is accurate to the package pin at the TX side accounting for all
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+ Skew + Skew
ClkRef
100 ps
(
+ 0,16,20,24,30 UI
(ps)
UserDataRate
+ Skew
USRCLKDiv Pkg
~70 ps
)
+ ------------------------------------------- -
UI
UserDataRate
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
R
UI
(ps)