Tx Low Latency Buffer Bypass Mode; Overview; Clocking - Xilinx Virtex-4 RocketIO User Manual

Chapter 8: Low-Latency Design

TX Low Latency Buffer Bypass Mode

Overview

For this mode, the TX Buffer is bypassed and TXSYNC must be used to synchronize the
PCS TXCLK and PMA TXCLK0. In this case, the phase alignment circuit requires the PCS
TXCLK to be the synchronization clock. This mode also results in channel to channel skew
reduction, but not as much as when GREFCLK is used as the synchronization source.
Table 8-9
the relevant MGT attribute settings. The attribute TXPHASESEL is used to select the
synchronization clock for the phase alignment circuit. The TXCLK0_FORCE_PMACLK
and TX_CLOCK_DIVIDER settings together determine the source of PCS TXCLK, which
can be generated either from the TX PMA parallel clock (PMA TXCLK0) or from the
internal PCS clock dividers. For low-latency buffer bypass mode, the PCS TXCLK must
always be sourced from the internal PCS Dividers. Refer to the figures in this section for
details.

Clocking

Figure 8-12
PCS TXCLK are sourced from the same PCS clock divider, the use of TX buffer is optional.
In these use models, PMA TXCLK0 is not used in the PCS. Since the PCS TXCLK domain
and the PMA TXCLK0 domain do not have a known phase relationship, the TX phase
alignment circuit in the TX PMA is used to eliminate the phase difference between the
clock domains and thus guarantee that setup and hold times are met at the PCS/PMA
boundary. For a good deskew result with these use models, it is recommended that the
same clock source be used to source TXUSRCLK2 on different channels.
As before, the phase alignment circuit adjusts the phase only of PMA TXCLK0 and not
TXOUTCLK1 when TXOUTCLK1 is sourced from the asynchronous PCS clock dividers. If
TXOUTCLK1 is to be used as the source for TXUSRCLK2 in Use Models TX_1x and TX_2x,
the asynchronous PCS clock dividers must be used. These dividers are not affected by the
phase alignment circuit. Doing this requires attributes TXCLKMODE[0] = 0,
TXCLKMODE[2] = 1, and TXOUTCLK1_USE_SYNC = FALSE.
TXUSRCLK2
In this mode, only the internal PCS dividers can be used for TXUSRCLK.
•
•
•
An external TXUSRCLK cannot be used in low-latency buffer bypass mode.
210
summarizes the use models of the TX PMA phase alignment circuit, along with
shows PCS TXCLK used as the synchronization clock. Since TXUSRCLK and
TXUSRCLK2
Clock Domain
PCS
Clock
Dividers
Figure 8-12: Using PCS TXCLK as Synchronization Clock (Use Models TX_3A-B)
If 4-byte mode is required, TX_CLOCK_DIVIDER = 11
If 2-byte mode is required, TX_CLOCK_DIVIDER = 01
If 1-byte mode is required, TX_CLOCK_DIVIDER = 10
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TXUSRCLK PCS TXCLK
Clock Domain Clock Domain
PCS TXCLK
TX RING
BUFFER
Virtex-4 RocketIO MGT User Guide
PMA TXCLK0
PMA Sync
Phase
Clock
Align
Dividers
TXCLK0
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UG076 (v4.1) November 2, 2008
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