User Guide Organization - Xilinx Virtex-4 RocketIO User Manual

Preface: About This Guide

User Guide Organization

This guide is organized as follows:
Section I: FPGA Level Design
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Section II: Board Level Design
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Section III: Appendixes
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Chapter 1, "RocketIO Transceiver Overview"
capabilities. Includes available ports, primitive and modifiable attributes, byte
mapping.
Chapter 2, "Clocking, Timing, and Resets"
examples for clocking/reset schemes.
Chapter 3, "PCS Digital Design Considerations"
level functions, 8B/10B encoding/decoding, comma detection, channel bonding,
status/event bus, loopback, digital receiver.
Chapter 4, "PMA Analog Design Considerations"
emphasis, differential receiver, analog functions.
Chapter 5, "Cyclic Redundancy Check
Chapter 6, "Analog and Board Design Considerations"
termination options, AC/DC coupling, high-speed trace design.
Chapter 7, "Simulation and Implementation"
implementation tools, debugging and diagnostics, transceiver locations, package pin
assignments.
Chapter 8, "Low-Latency Design"
Chapter 9, "Methodology Overview"
Chapter 10, "PCB Materials and Traces"
characteristics to maximize signal integrity.
Chapter 11, "Design of Transitions"
their effect on signal integrity, impedance, and differential balance.
Chapter 12, "Guidelines and Examples"
design success.
Appendix A, "RocketIO Transceiver Timing Model"
with the MGT core.
Appendix B, "8B/10B Valid Characters"
Appendix C, "Dynamic Reconfiguration Port"
dynamically configuring the attribute settings. (For advanced users.)
Appendix D, "Special Analog Functions"
function.
Appendix E, "Virtex-II Pro/Virtex-II Pro X to Virtex-4 RocketIO Transceiver Design
Migration" – Important differences to be aware of when migrating designs from
Virtex-II Pro/ Virtex-II Pro X to Virtex-4 FPGAs.
Appendix F, "References"
www.xilinx.com
– MGT basic architecture and
– Clock domain architecture, clock ports,
– Top-level architecture and block-
– Serial I/O, output swing and
(CRC)"– CRC functionality, latency, timing.
– Power requirements,
– Simulation models/considerations,
– Details of designing for minimum latency.
– Powering, clocking, and coupling MGTs.
– Handling PCB and interconnect
– Detailed analysis of PCB trace geometries and
– Practical guidelines for maximizing PCB
– Timing parameters associated
– Valid data and K-character table.
– Parallel programming bus for
– Receiver Sample Phase Adjustment
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
R