Selectio-To-Mgt Crosstalk - Xilinx Virtex-4 RocketIO User Manual

Chapter 6: Analog and Board Design Considerations

SelectIO-to-MGT Crosstalk

Since it is possible that MGT performance can degrade in an environment flooded with
SelectIO™ activity, it is important to have guidelines for SelectIO usage which minimize
the impact on MGT performance.
Although the Virtex-4 FX package itself exhibits little package-related crosstalk issues, the
pinout of the device might lead to customer designs becoming susceptible to PCB-via-
related crosstalk issues. The near proximity of SelectIO signals (aggressor) to MGT analog
supplies (victim) results in their PCB via structures being placed in close proximity as well.
This BGA adjacency and resulting via adjacency creates a via-coupling region between the
SelectIO and the MGT analog supplies that is not accounted for by on-board power supply
filtering. The amount of crosstalk voltage induced on the victim circuit by the aggressor
circuit is equal to the rate of change of current in the aggressor times the mutual inductance
shared between the two circuits. For an in-depth discussion on via crosstalk and
calculations of mutual inductance for various via configurations, please refer to High-Speed
Signal Propagation: Advanced Black Magic by Howard Johnson and Martin Graham. The
sensitivity of the MGT analog supplies to coupled noise from the PCB results in a
degradation of MGT performance. To minimize the impact on MGT performance, consider
the following list of BGA adjacency guidelines:
•
•
•
•
•
The absolute worst-case scenario would be to supply MGT analog supplies from the
bottom of the board and have all adjacent SelectIO outputs running at high drive/high
speed and routed to lower routing layers. For more information, please refer to
Escape Example" in the BGA Escape Example section of Chapter 12
escaping of SIO adjacent to MGT analog supply pins.
SelectIO having the largest impact on MGT performance are those whose solder balls are
adjacent to MGT analog supply solder balls (BGA Adjacency) and those that have package
core vias adjacent to analog supply package core vias (Core Via).
Table 6-5
optimize MGT performance in the presence of SelectIO switching. Specifically, the tables
identify those pins which are either 1.0 mm or 1.4 mm away from an MGT analog supply
pin. If a pin is both 1.0 mm and 1.4 mm away from two different MGT analog supply pins,
then it is only listed in the 1.0 mm column. In addition, the table also lists those pins which
have package core vias which are adjacent to analog supply package core vias.
174
Avoid utilizing SelectIO nets 1.0 mm or 1.4 mm away from MGT analog power supply
pins. Ground these SelectIO locations in the PCB, and set the SelectIO output to
highest drive and a forced-Low setting.
If these SelectIO outputs must be used, use them for static control/status signals, low-
speed/low-drive, or differential signaling applications.
If these SelectIO pins must be used for higher drive/higher speed applications, apply
power to the MGT analog supplies with a plane or wide buses a few layers below the
top of the board. Using a blind via to the MGT analog supplies is better than using a
through via.
If a through via to supply the MGT analog supply pins must be used, use an upper
layer to supply analog power to these vias. Route SelectIO nets in the uppermost layer
available after MGT signal and MGT analog supply routing is implemented.
If supplying MGT power from the bottom of the board, route these SelectIO nets in
the highest available routing layer.
provide the RocketIO MGT user with pin-specific guidance recommendations to
www.xilinx.com
"BGA
for information on
Table 6-3 through
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
R