Bus Interface; External Bus Width Configuration (Fabric Interface) - Xilinx Virtex-4 RocketIO User Manual

Multi-gigabit transceiver
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R
The overflow mark is set when the difference between the write and read pointer is greater
than 57 bytes. The underflow mark is set when the difference between the write and read
pointer is less than 17 bytes. These cases are illustrated in
An overflow or underflow on the RX ring buffer causes RXBUFERR to go High.

Bus Interface

External Bus Width Configuration (Fabric Interface)

The fabric interface module resides in the PCS portion of the MGT. The PCS is divided into
transmit (TX) and receive (RX) blocks. Separate fabric interface blocks reside in TX and RX
blocks.
The PCS TX fabric interface is used to transform data from the fabric clock domain
(TXUSRCLK2) to the internal PCS clock domain (TXUSRCLK). The internal PCS data path
is 4 bytes (32/40 bits) wide. The TX fabric interface aggregates user data if the fabric clock
domain is higher frequency (narrower bus width: one or two byte mode) than the internal
clock domain. It distributes data if the fabric clock domain is slower (eight byte mode) than
the internal clock domain. The RX fabric interface distributes user data if the fabric clock
domain is higher frequency (narrower bus width: one or two byte mode) than internal
clock domain. It aggregates data if the fabric clock domain is slower (eight byte mode) than
the internal clock domain.
By using the signals TXDATAWIDTH[1:0] and RXDATAWIDTH[1:0], the fabric interface
can be determined. This also determines the USRCLK and USRCLK2 relationships. For
slower serial speeds, 1-byte and 2-byte interfaces are preferred. For higher serial rates,
4-byte and 8-byte interfaces are recommended.
Table 3-2
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
RX Ring Buffer
Data
64
rd_ptr
Figure 3-4: RX Ring Buffer Overflow and Underflow
shows the available external (fabric interface) bus width settings.
www.xilinx.com
Figure
wr_ptr
57
(Buffer
overflows
at > 57)
32
64
rd_ptr
Bus Interface
3-4:
RX Ring Buffer
32
wr_ptr
17
(Buffer
Data
underflows
at < 17)
ug076_ch3_42_060107
103

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