Fabric Interface Synchronicity; Rx Buffer - Xilinx Virtex-4 RocketIO User Manual

Chapter 3: PCS Digital Design Considerations
RXUSRCLK
RXRECCLK1/
RXRECCLK2
Raw SERDES /
PCS-Bypass
RXDATA
Note: (1) 64B/66B encoding/decoding is not supported.

Fabric Interface Synchronicity

The fabric interface affords a clock domain crossing between RX/TXUSRCLK and
RX/TXUSRCLK2. To minimize latency, this cross-clock domain crossing is synchronous
and does not use a buffer. This implementation mandates that the TX/RXUSRCLK and
TX/RXUSRCLK2 be positive-edge aligned.

RX Buffer

The buffer is 64 bits deep by 13 bits. The 13 bits include each byte of data (either 8 bits or
10 bits, depending upon the data path size) plus a number of status bits.
The RX ring buffer goes to half-full upon initialization or reset (RXRESET = 1), as
illustrated in
102
PMA RXCLK
Sync State Machine
SLIP
Comma 64B/66B
Detect Block
(1)
Align Sync
Decoders &
Ring Buffer
Bypass RXDATA
RXDEC8B10BUSE
RXDESCRAM64B66BUSE
RXBLOCKSYNC64B66BUSE
RXCOMMADETUSE
Figure 3-2: Receive Architecture
Figure 3-3.
RX Ring Buffer
64
Figure 3-3: RX Ring Buffer Half-Full Upon Initialization
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Channel Bonding & Clock
Correction
8B/10B
Decode
RX Ring
64B/66B
Buffer
(1)
Descr
13x64
Ring Buffer
Bypass RXDATA
RX_BUFFER_USE
10GBASE-R Decoder
Bypass RXDATA
(used for all protocols
not wanting to use the
64B/66B decoder.)
57
(Buffer
overflows
at > 57)
32
17
(Buffer
underflows
at < 17)
ug076_ch3_41_060107
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
R
Reset Control
10GBASE-R
(1)
Decode
RXDATA
RXUSRCLK
RXUSRCLK2
(1)
RXDEC64B66BUSE
RXDATA_SEL
ug035_ch3_02_071807