Xilinx Virtex-4 RocketIO User Manual page 45

R
Table 1-6: RocketIO MGT PCS Ports (Continued)
Port
TXCHARISK
TXENC8B10BUSE
TXKERR
TXRUNDISP
Alignment
ENMCOMMAALIGN
ENPCOMMAALIGN
RXCOMMADET
RXCOMMADETUSE
RXREALIGN
RXSLIDE
Data Path
RXDATA
RXDATAWIDTH
RXINTDATAWIDTH
TXDATA
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
I/O Port Size
If TXENC8B10BUSE = 1 (8B/10B encoder enable), then
I 8 TXCHARISK[7:0] signals the K-definition of the TXDATA byte
in the corresponding byte lane.
If set to a logic 1, the 8B/10B encoder is used. If set to a logic 0,
I 1
the 8B/10B encoder is bypassed.
In 8B/10B mode, indicates that an invalid K-character was
O 8
transmitted.
Signals the running disparity (0 = negative, 1 = positive) for its
O 8
corresponding byte after that byte is encoded.
Selects realignment of incoming serial bitstream on minus-
I 1 comma. When set to logic 1, realigns serial bitstream byte
boundary to where minus-comma is detected.
Selects realignment of incoming serial bitstream on plus-
I 1 comma. When set to logic 1, realigns the serial bitstream byte
boundary to where plus-comma is detected.
Indicates that the symbol defined by PCOMMA_32B_VALUE
(if PCOMMA_DETECT is asserted) and/or
O 1
MCOMMA_32B_VALUE (if MCOMMA_DETECT is asserted)
has been received.
If set to a logic 1, the comma detect is used. If set to a logic 0,
I 1
the comma detect is bypassed.
Signal from the PCS data aligner denoting that the byte
O 1 alignment with the serial data stream changed due to a comma
detection. Raised to a logic 1 when alignment occurs.
Enables the "slip" of the PCS alignment block by 1 bit. To
enable a slide of 1 bit, it increments from a lower bit to a higher
bit. This signal must be set to logic 1 for at least one clock cycle
I 1
and then set to a logic 0 synchronous to RXUSRCKLK2.
RXSLIDE must be held Low for at least three RXUSRCLK2
clock cycles before being set to a logic 1 again.
Receive data at the FPGA user fabric. RXDATA[7:0] is always
O 64
the first byte received.
Indicates width of FPGA parallel bus. (See
I 2
page 104.)
Sets the internal mode of the receive PCS:
I 2
2'b10 = 32-bit
2'b11 = 40-bit
Transmit data from the FPGA user fabric that is 8 bytes wide.
I 64
TXDATA[7:0] is always the first byte transmitted.
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Available Ports
Definition
Table 3-1,
45