Tx Low Latency Buffered Mode With Channel Deskew; Overview; Clocking - Xilinx Virtex-4 RocketIO User Manual

Chapter 8: Low-Latency Design

TX Low Latency Buffered Mode with Channel Deskew

Overview

For this mode, the TXSYNC functionality is required to synchronize the PCS and PMA
clocks across all channels that need to be deskewed.
Transmitters in different MGT tiles are not inherently aligned, as their TX PMA parallel
clocks are generated from independent PLLs. The phase alignment circuit aligns the phase
of the PMA parallel clocks in multiple transceivers, thus reducing the skew seen at the
serial TX outputs.

Clocking

Figure 8-3
unknown phase relationship to the PCS TXCLK domain, the phase alignment circuit using
GREFCLK inherits the phase uncertainty and passes it to the TX PMA parallel clock (PMA
TXCLK0). The user must then source the PCS TXCLK with PMA TXCLK0 and use the TX
buffer to compensate for the phase difference between the TXUSRCLK and PCS TXCLK
clock domains. The frequency of GREFCLK must be equal to or less than the frequency of
TXUSRCLK. At the same time, GREFCLK can be used as the TX PLL reference clock.
The setting of TXABPMACLKSEL does not affect the operation of the phase alignment
circuit. The phase alignment circuit adjusts the phase only of PMA TXCLK0 and not
TXOUTCLK1 as long as TXOUTCLK1 is sourced from the asynchronous PMA clock
dividers (not the synchronous dividers). If TXOUTCLK1 is to be used as the source for
TXUSRCLK2 in Use Models TX_1x and TX_2x, the asynchronous PCS clock dividers must
be used. These dividers are not affected by the phase alignment circuit. Doing this requires
attributes TXCLKMODE[0] = 0, TXCLKMODE[2] = 1, and TXOUTCLK1_USE_SYNC =
FALSE.
GREFCLK's limitation of 1 Gb/s does not apply if it is only being used as an alignment
reference. For data rates greater than 1 Gb/s, GREFCLK can be used as the alignment
reference and MGTCLK can be used as the TX PLL reference clock.
Use Models TX_2A through TX_2D illustrate the use of internal PCS clock dividers,
whereas Use Models TX_2E through TX_2H illustrate the use of an external clock to drive
the TXUSRCLK port.
This function is recommended for standards such as SFI4.2, where there is a specified
maximum channel skew and no inherent channel bonding functionality.
TXUSRCLK2
TXUSRCLK
200
shows GREFCLK used as the synchronization clock. Since GREFCLK has an
TXUSRCLK2
Clock Domain
PCS
Clock
Dividers
Figure 8-3: Using GREFCLK as Synchronization Clock (Use Models TX_2A-H)
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TXUSRCLK PCS TXCLK
Clock Domain Clock Domain
TX RING
BUFFER
Virtex-4 RocketIO MGT User Guide
GREFCLK
PMA TXCLK0
PMA Sync
Phase
Clock
Align
Dividers
TXCLK0
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