Xilinx Virtex-4 RocketIO User Manual page 59

R
Table 1-12: RocketIO MGT PCS Attributes (Continued)
Attribute
Bypass Controls
RXDATA_SEL
TXDATA_SEL
Notes:
1. 64B/66B encoding/decoding is not supported.
Table 1-13: RocketIO MGT Digital Receiver Attributes
Attribute
DCDR_FILTER
DIGRX_FWDCLK
DIGRX_SYNC_MODE
ENABLE_DCDR
RXBY_32
RXDIGRX
SAMPLE_8X
RXDIGRESET
Notes:
1. Buffer bypass mode used in conjunction with the digital receiver is not supported. DIGRX_SYNC_MODE must always be set to
FALSE.
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
Type
Selects which blocks are bypassed in the RX PCS data path. See
2-bit
"Ports and Attributes"
Binary
more details.
Selects which blocks are bypassed in the TX PCS data path. See
2-bit
"Ports and Attributes"
Binary
more details.
Type
3-bit
Attribute should be set to 000.
Binary
2-bit Selects receiver output clock when ENABLE_DCDR is TRUE. See
Binary Chapter 2, "Clocking, Timing, and Resets"
FALSE/TRUE.
FALSE: Disables the RX phase aligner. Should be set FALSE when
Boolean RX Buffer is to be used.
TRUE: Enables the RX phase aligner. Should be set TRUE when
RX Buffer is to be bypassed
FALSE/TRUE. Select clock and data recovery (CDR) mode. Enables
the digital oversampling receiver.
Boolean
FALSE: Disables the oversampled digital receiver.
TRUE: Enables the oversampled digital receiver for data rates of
1.25 Gb/s and below.
FALSE/TRUE. Determines if internal data path is 40 or 32 bits for the
digital receiver.
Boolean
FALSE: 40
TRUE: 32
FALSE/TRUE. Select clock and data recovery (CDR) mode.
FALSE: Allows PLL switch to lock to received data after lock to
Boolean the reference clock for data rates greater than 1.25 Gb/s.
TRUE: Enables PLL to lock continuously to the reference clock for
data rates of 1.25 Gb/s and below.
FALSE/TRUE. Determines the type of oversampling that is
Boolean implemented in the digital receiver. This should always be set to
TRUE.
FALSE/TRUE. Resets the deserializer.
Boolean
FALSE: Enable receiver deserializer.
TRUE: Reset receiver deserializer.
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Description
in Chapter 8, "Low-Latency Design"
in Chapter 8, "Low-Latency Design"
Description
for details.
(1)
.
Attributes
for
for
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