Implementation - Xilinx Virtex UltraScale+ FPGAs User Manual

Implementation

It is a common practice to define the location of GTM transceiver Duals early in the design
process to ensure correct usage of clock resources and to facilitate signal integrity analysis during
board design. The implementation flow facilitates this practice through the use of location
constraints in the XDC file.
The position of each GTM transceiver Dual primitive is specified by an XY coordinate system that
describes the column number and the relative position within that column. For a given device/
package combination, the transceiver with the coordinates X0Y0 is located at the lowest position
of the lowest available bank.
There are two ways to create an XDC file for designs that utilize the GTM transceivers. The
preferred method is to use the UltraScale+ FPGAs GTM Transceivers Wizard. The Wizard
automatically generates XDC file templates that configure the transceivers and contain
placeholders for GTM transceiver placement information. The XDC files generated by the Wizard
can then be edited to customize operating parameters and placement information for the
application.
The second approach is to create the XDC file manually. When using this approach, you must
enter both configuration attributes that control transceiver operation as well as the location
parameters. Care must be taken to ensure that all of the parameters needed to configure the
GTM transceiver are correctly entered. A GTM_DUAL primitive must be instantiated as shown in
the following figure.
One-Dual, Two-Channel Configuration (Reference Clock from the LCPLL)
Figure 3:
IBUFDS_GTM
Each dual contains an LCPLL. Therefore, a reference clock can be connected directly to a
GTM_DUAL primitive.
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
Chapter 1: Transceiver and Tool Overview
GTM_DUAL
LCPLL
GTM Channel 0 (CH0)
TX
RX
GTM Channel 1 (CH1)
TX
RX
www.xilinx.com
Send Feedback
X20212-061418
11