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Xilinx RocketIO User Manual

Xilinx RocketIO User Manual

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RocketIO™
Transceiver

User Guide

UG024 (v3.0) February 22, 2007
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  • Page 1: User Guide

    Product Not Recommended for New Designs RocketIO™ Transceiver User Guide UG024 (v3.0) February 22, 2007...
  • Page 2 Xilinx, Inc. assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction if such be made. Xilinx, Inc. will not assume any liability for the accuracy or correctness of any engineering or software support or assistance provided to a user.
  • Page 3 Product Not Recommended for New Designs RocketIO™ Transceiver User Guide UG024 (v3.0) February 22, 2007 The following table shows the revision history for this document. Date Version Revision • Initial Xilinx release. 11/20/01 • Updated for typographical and other errors found during review.
  • Page 4 1-2: Added qualifying footnote to XAUI 10GFC. • Table 1-5: Corrected definition of RXRECCLK. • Section “RocketIO Transceiver Instantiations” in Chapter 1: added text briefly explaining what the Instantiation Wizard does. • Table 2-14: Changed numerics from exact values to rounded-off approximations (nearest 5,000), and added footnote calling attention to this.
  • Page 5 • Section “Voltage Regulation” in Chapter 3: Added Linear Technology part numbers (LT1963A, LT1964). • Section “Passive Filtering” in Chapter 3: Added new cap rules for RocketIO transceiver. • Figure 3-8, page 111: Replaced old Figure 3-8 with new figure showing “Power Filtering Network on Devices with Internal and External Capacitors.”...
  • Page 6 111: Corrected part number of Murata ferrite bead. • “Pletronics LV1145B (LVDS Outputs),” page 119: Corrected I/O standard name to LVDS_25_DT. • “Powering the RocketIO Transceivers,” page 120: Added section “Pin Connections on the Unused RocketIO Transceivers.” • “The POWERDOWN Port,” page 120: Added that toggling POWERDOWN properly initializes the PMA.

  • Page 7: Table Of Contents

    Online Document ............20 Chapter 1: RocketIO Transceiver Overview Basic Architecture and Capabilities .
  • Page 8 Overview ..............76 www.xilinx.com RocketIO™ Transceiver User Guide UG024 (v3.0) February 22, 2007...
  • Page 9 RocketIO CRC Support Limitations ........
  • Page 10 Powering the RocketIO Transceivers ........
  • Page 11 Embedded RocketIO Transceivers ........
  • Page 12 Product Not Recommended for New Designs www.xilinx.com RocketIO™ Transceiver User Guide UG024 (v3.0) February 22, 2007...

  • Page 13: Schedule Of Figures

    Figure 1-1: RocketIO Transceiver Block Diagram ....... . . 22...
  • Page 14 Appendix A: RocketIO Transceiver Timing Model Figure A-1: RocketIO Transceiver Block Diagram ....... 128 Figure A-2: RocketIO Transceiver Timing Relative to Clock Edge .

  • Page 15: Schedule Of Tables

    Chapter 1: RocketIO Transceiver Overview Table 1-1: Number of RocketIO Cores per Device Type ......21 Table 1-2: Communications Standards Supported by RocketIO Transceiver .
  • Page 16 Table A-1: RocketIO Clock Descriptions ........

  • Page 17: Preface: About This Guide

    Product Not Recommended for New Designs Preface About This Guide The RocketIO Transceiver User Guide provides the product designer with the detailed technical information needed to successfully implement the RocketIO™ multi-gigabit transceiver in Virtex-II Pro Platform FPGA designs. RocketIO Features The RocketIO transceiver’s flexible, programmable features allow a multi-gigabit serial...

  • Page 18: For More Information

    Appendix C, “Related Online Documents” — Bibliography of online Application Notes, Characterization Reports, and White Papers. For More Information For a complete menu of online information resources available on the Xilinx website, visit http://www.xilinx.com/virtex2pro/ or refer to Appendix C, “Related Online Documents.”...

  • Page 19: Conventions

    Port and Attribute Names Input and output ports of the RocketIO transceiver primitives are denoted in upper-case letters. Attributes of the RocketIO transceiver are denoted in upper-case letters with underscores. Trailing numbers in primitive names denote the byte width of the data path.

  • Page 20: Online Document

    Cross-reference link to a Figure 2-5 in the Virtex-II Red text location in another document Handbook. Go to http://www.xilinx.com Blue, underlined text Hyperlink to a website (URL) for the latest speed files. www.xilinx.com RocketIO™ Transceiver User Guide UG024 (v3.0) February 22, 2007...

  • Page 21: Basic Architecture And Capabilities

    Product Not Recommended for New Designs Chapter 1 RocketIO Transceiver Overview Basic Architecture and Capabilities The RocketIO transceiver is based on Mindspeed’s SkyRail™ technology. Figure 1-1, page 22, depicts an overall block diagram of the transceiver. Up to 20 transceiver modules are available on a single Virtex-II Pro FPGA, depending on the part being used.
  • Page 22 TXINHIBIT LOOPBACK[1:0] TXRESET RXRESET REFCLK REFCLK2 GNDA TX/RX GND REFCLKSEL BREFCLK AVCCAUXTX 2.5V TX BREFCLK2 RXUSRCLK VTTX Termination Supply TX RXUSRCLK2 TXUSRCLK TXUSRCLK2 DS083-2_04_090402 Figure 1-1: RocketIO Transceiver Block Diagram www.xilinx.com RocketIO™ Transceiver User Guide UG024 (v3.0) February 22, 2007...

  • Page 23: Rocketio Transceiver Instantiations

    • Dynamic changes can be made by the ports of the primitives The RocketIO transceiver consists of the Physical Media Attachment (PMA) and Physical Coding Sublayer (PCS). The PMA contains the serializer/deserializer (SERDES), TX and RX buffers, clock generator, and clock recovery circuitry. The PCS contains the 8B/10B encoder/decoder and the elastic buffer supporting channel bonding and clock correction.

  • Page 24: List Of Available Ports

    Chapter 1: RocketIO Transceiver Overview List of Available Ports The RocketIO transceiver primitives contain 50 ports, with the exception of the 46-port GT_ETHERNET and GT_FIBRE_CHAN primitives. The differential serial data ports (RXN, RXP, TXN, and TXP) are connected directly to external pads; the remaining 46 ports are all accessible from the FPGA logic (42 ports for GT_ETHERNET and GT_FIBRE_CHAN).
  • Page 25 8, 16, 32 Up to four bytes of decoded (8B/10B encoding) or encoded (8B/10B bypassed) receive data. RXDISPERR 1, 2, 4 If 8B/10B encoding is enabled it indicates whether a disparity error has occurred on the serial line. Included in Byte-mapping scheme. RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v3.0) February 22, 2007...
  • Page 26 Product Not Recommended for New Designs Chapter 1: RocketIO Transceiver Overview Table 1-5: GT_CUSTOM , GT_AURORA, GT_FIBRE_CHAN , GT_ETHERNET GT_INFINIBAND, and GT_XAUI Primitive Ports (Continued) Port Port Definition Size RXLOSSOFSYNC Status related to byte-stream synchronization (RX_LOSS_OF_SYNC_FSM) If RX_LOSS_OF_SYNC_FSM = TRUE, RXLOSSOFSYNC indicates the...
  • Page 27 Clock output from a DCM or a BUFG that is clocked with a reference clock. This clock is used for writing the TX buffer and is frequency- locked to the reference clock. RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v3.0) February 22, 2007...
  • Page 28 Product Not Recommended for New Designs Chapter 1: RocketIO Transceiver Overview Table 1-5: GT_CUSTOM , GT_AURORA, GT_FIBRE_CHAN , GT_ETHERNET GT_INFINIBAND, and GT_XAUI Primitive Ports (Continued) Port Port Definition Size TXUSRCLK2 Clock output from a DCM that clocks transmission data and status and reconfiguration data between the transceiver an the FPGA core.

  • Page 29: Primitive Attributes

    Table 1-6 shows a brief description of each attribute. Table 1-7 Table 1-8 have the default values of each primitive. Table 1-6: RocketIO Transceiver Attributes Attribute Description ALIGN_COMMA_MSB TRUE/FALSE controls the alignment of detected commas within the transceiver’s 2-byte-wide data path.
  • Page 30 Product Not Recommended for New Designs Chapter 1: RocketIO Transceiver Overview Table 1-6: RocketIO Transceiver Attributes (Continued) Attribute Description CHAN_BOND_OFFSET Integer 0-15 that defines offset (in bytes) from channel bonding sequence for realignment. It specifies the first elastic buffer read address that all channel- bonded transceivers have immediately after channel bonding.
  • Page 31 Product Not Recommended for New Designs Primitive Attributes Table 1-6: RocketIO Transceiver Attributes (Continued) Attribute Description CLK_COR_INSERT_IDLE_FLAG TRUE/FALSE controls whether RXRUNDISP input status denotes running disparity or inserted-idle flag. FALSE: RXRUNDISP denotes running disparity when RXDATA is decoded data. TRUE: RXRUNDISP is raised for the first byte of each inserted (repeated) clock correction (“Idle”) sequence (when RXDATA is decoded data).
  • Page 32 Product Not Recommended for New Designs Chapter 1: RocketIO Transceiver Overview Table 1-6: RocketIO Transceiver Attributes (Continued) Attribute Description CRC_END_OF_PKT NOTE: This attribute is only valid when CRC_FORMAT = USER_MODE. K28_0, K28_1, K28_2, K28_3, K28_4, K28_5, K28_6, K28_7, K23_7, K27_7, K29_7, K30_7.
  • Page 33 Product Not Recommended for New Designs Primitive Attributes Table 1-6: RocketIO Transceiver Attributes (Continued) Attribute Description RX_BUFFER_USE Always set to TRUE. RX_CRC_USE, TRUE/FALSE determines if CRC is used or not. TX_CRC_USE RX_DATA_WIDTH, Integer (1, 2, or 4). Relates to the data width of the FPGA fabric interface.

  • Page 34: Modifiable Primitives

    Product Not Recommended for New Designs Chapter 1: RocketIO Transceiver Overview Modifiable Primitives As shown in Table 1-7 Table 1-8, only certain attributes are modifiable for any primitive. These attributes help to define the protocol used by the primitive. Only the GT_CUSTOM primitive allows the user to modify all of the attributes to a protocol not supported by another transceiver primitive.
  • Page 35 FALSE FALSE RX_DATA_WIDTH RX_DECODE_USE TRUE TRUE TRUE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM TRUE TRUE TRUE SERDES_10B FALSE FALSE FALSE TERMINATION_IMP TX_BUFFER_USE TRUE TRUE TRUE TX_CRC_FORCE_VALUE 11010110 11010110 11010110 TX_CRC_USE FALSE FALSE FALSE RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v3.0) February 22, 2007...
  • Page 36 Product Not Recommended for New Designs Chapter 1: RocketIO Transceiver Overview Table 1-7: Default Attribute Values: GT_AURORA, GT_CUSTOM, GT_ETHERNET (Continued) Default Default Default Attribute GT_AURORA GT_CUSTOM GT_ETHERNET TX_DATA_WIDTH TX_DIFF_CTRL TX_PREEMPHASIS Notes: All GT_CUSTOM attributes are modifiable. Modifiable attribute for specific primitives.
  • Page 37 Lane ID(INFINBAND ONLY) 00000000000 MCOMMA_10B_VALUE 1100000000 1100000000 1100000000 MCOMMA_DETECT TRUE TRUE TRUE PCOMMA_10B_VALUE 0011111000 0011111000 0011111000 PCOMMA_DETECT TRUE TRUE TRUE REF_CLK_V_SEL RX_BUFFER_USE TRUE TRUE TRUE RX_CRC_USE FALSE FALSE FALSE RX_DATA_WIDTH RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v3.0) February 22, 2007...

  • Page 38: Byte Mapping

    Product Not Recommended for New Designs Chapter 1: RocketIO Transceiver Overview Table 1-8: Default Attribute Values: GT_FIBRE_CHAN, GT_INFINIBAND, and GT_XAUI (Continued) Default Default Default Attribute GT_FIBRE_CHAN GT_INFINIBAND GT_XAUI RX_DECODE_USE TRUE TRUE TRUE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM TRUE TRUE TRUE SERDES_10B FALSE...

  • Page 39: Chapter 2: Digital Design Considerations

    FPGA as differential inputs. The reference clocks connect to the REFCLK or BREFCLK ports of the RocketIO multi-gigabit transceiver (MGT). While only one of these reference clocks is needed to drive the MGT, BREFCLK or BREFCLK2 must be used for serial speeds of 2.5 Gb/s or greater.
  • Page 40 1. Because of dedicated routing to reduce jitter, BREFCLK cannot be routed through the fabric. 2. While this option is available in the silicon, this topography adds extra jitter to the reference clock which can affect the overall performance of the transceiver. www.xilinx.com RocketIO™ Transceiver User Guide UG024 (v3.0) February 22, 2007...

  • Page 41: Brefclk

    Clocking BREFCLK At speeds of 2.5 Gb/s or greater, REFCLK configuration introduces more than the maximum allowable jitter to the RocketIO transceiver. For these higher speeds, BREFCLK configuration is required. The BREFCLK configuration uses dedicated routing resources that reduce jitter.

  • Page 42: Clock Ratio

    TXUSRCLK, TXUSRCLK2, etc. in the FPGA core and REFCLK at the pad. NOTE: The reference clock may be any of the four MGT clocks, including the BREFCLKs. www.xilinx.com RocketIO™ Transceiver User Guide UG024 (v3.0) February 22, 2007...

  • Page 43: Example 1A: Two-Byte Clock With Dcm

    DCM for 2-byte GT -- Device: Virtex-II Pro Family --------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; -- pragma translate_off library UNISIM; use UNISIM.VCOMPONENTS.ALL; -- pragma translate_on entity TWO_BYTE_CLK is port ( REFCLKIN : in std_logic; RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v3.0) February 22, 2007...
  • Page 44 : out std_logic; STATUS : out std_logic_vector ( 7 downto 0 ) end component; -- Signal Declarations: signal GND : std_logic; signal CLK0_W : std_logic; begin <= '0'; -- DCM Instantiation www.xilinx.com RocketIO™ Transceiver User Guide UG024 (v3.0) February 22, 2007...
  • Page 45 REFCLKIN; output REFCLK; output USRCLK_M; output DCM_LOCKED; wire REFCLKIN; wire REFCLK; wire USRCLK_M; wire DCM_LOCKED; wire REFCLKINBUF; wire clk_i; DCM dcm1 ( .CLKFB ( USRCLK_M ), .CLKIN ( REFCLKINBUF ), RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v3.0) February 22, 2007...

  • Page 46: Example 1B: Two-Byte Clock Without Dcm

    The DCM example (Figure 2-4) is detailed for a 4-byte data path. If 3.125 Gb/s is required, REFCLK is 156 MHz and USRCLK2_M runs at only 78 MHz, including the clocking for www.xilinx.com RocketIO™ Transceiver User Guide UG024 (v3.0) February 22, 2007...
  • Page 47 : out std_logic end FOUR_BYTE_CLK; architecture FOUR_BYTE_CLK_arch of FOUR_BYTE_CLK is -- Components Declarations: component BUFG port ( I : in std_logic; O : out std_logic end component; component IBUFG port ( RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v3.0) February 22, 2007...
  • Page 48 => GND, PSEN => GND, PSCLK => GND, => RST, CLK0 => CLK0_W, CLKDV => CLKDV_W, LOCKED => LOCK -- BUFG Instantiation U_BUFG: IBUFG port map ( I => REFCLKIN, www.xilinx.com RocketIO™ Transceiver User Guide UG024 (v3.0) February 22, 2007...
  • Page 49 ( REFCLKINBUF ) , .DSSEN ( 1'b0 ), .PSCLK ( 1'b0 ), .PSEN ( 1'b0 ), .PSINCDEC ( 1'b0 ), .RST ( 1'b0 ), .CLK0 ( clk_i ), .CLK90 ( ), RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v3.0) February 22, 2007...

  • Page 50: Example 3: One-Byte Clock

    CLK0 BUFG UG024_04_112202 Figure 2-5: One-Byte Clock VHDL Template -- Module: ONE_BYTE_CLK -- Description: VHDL submodule DCM for 1-byte GT -- Device: Virtex-II Pro Family --------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; www.xilinx.com RocketIO™ Transceiver User Guide UG024 (v3.0) February 22, 2007...
  • Page 51 CLKFX : out std_logic; CLKFX180 : out std_logic; LOCKED : out std_logic; PSDONE : out std_logic; STATUS : out std_logic_vector ( 7 downto 0 ) end component; -- Signal Declarations: RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v3.0) February 22, 2007...
  • Page 52 I => CLK2X180_W, O => USRCLK2_M_W end ONE_BYTE_CLK_arch; Verilog Template // Module: ONE_BYTE_CLK // Description: Verilog Submodule DCM for 1-byte GT // Device: Virtex-II Pro Family module ONE_BYTE_CLK ( REFCLKIN, REFCLK, www.xilinx.com RocketIO™ Transceiver User Guide UG024 (v3.0) February 22, 2007...
  • Page 53 .I ( clk2x_180 ), .O ( USRCLK2_M ) BUFG buf2 ( .I ( clk_i ), .O ( USRCLK_M ) IBUFGbuf3 ( .I ( REFCLKIN ), .O ( REFCLKINBUF ) endmodule RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v3.0) February 22, 2007...

  • Page 54: Half-Rate Clocking Scheme

    REFCLK REFCLK_P REFCLK CLKIN CLK_FX180 TXUSRCLK REFCLK_N RXUSRCLK BUFG TXUSRCLK2 TXUSRCLK RXUSRCLK2 CLKDV RXUSRCLK BUFG TXUSRCLK2 CLK0 CLKFB RXUSRCLK2 BUFG UG024_31_013103 Figure 2-8: Four-Byte Data Path Clocks, SERDES_10B = TRUE www.xilinx.com RocketIO™ Transceiver User Guide UG024 (v3.0) February 22, 2007...

  • Page 55: Multiplexed Clocking Scheme With Dcm

    DCMs. The clocks are then multiplexed before input into the RocketIO transceiver. User logic can be designed to determine during auto negotiation if the reference clock used for the transceiver is incorrect.

  • Page 56: Rxrecclk

    For specific timing values, see Module 3 of the Virtex-II Pro data sheet. The timing relationships are further discussed and illustrated in Appendix A, “RocketIO Transceiver Timing Model.” www.xilinx.com RocketIO™ Transceiver User Guide UG024 (v3.0) February 22, 2007...

  • Page 57: Data Path Latency

    This allows the elastic buffer to be cleared in case of an over/underflow without affecting the ongoing TX transmission. The following example is an implementation that resets all three data-width transceivers. RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v3.0) February 22, 2007...
  • Page 58 USRCLK2_M : in std_logic; LOCK : in std_logic; REFCLK : out std_logic; DCM_LOCKED: in std_logic; : out std_logic); end gt_reset; architecture RTL of gt_reset is signal startup_count : std_logic_vector (7 downto 0); begin www.xilinx.com RocketIO™ Transceiver User Guide UG024 (v3.0) February 22, 2007...
  • Page 59 <= startup_counter + 1; always @ ( posedge USRCLK2_M or negedge DCM_LOCKED ) if ( !DCM_LOCKED ) RST <= 1'b1; else RST <= ( startup_counter != 8'h02 ); endmodule RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v3.0) February 22, 2007...

  • Page 60: 8B/10B Encoding/Decoding

    Chapter 2: Digital Design Considerations 8B/10B Encoding/Decoding Overview The RocketIO transceiver has the ability to encode eight bits into a 10-bit serial stream using standard 8B/10B encoding. This guarantees a DC-balanced, edge-rich serial stream, facilitating DC- or AC-coupling and clock recovery.

  • Page 61: Ports And Attributes

    Transmitter Channel Bonding 20X Multiplier Clock Correction Receiver RX Clock Recovery 32/16/8 bits 8B/10B Elastic Receive RXDATA Deserializer Decode Buffer Buffer RX− Comma Detect UG024_09_020507 Figure 2-12: 8B/10B Data Flow RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v3.0) February 22, 2007...

  • Page 62: Txchardispval, Txchardispmode

    High, the running disparity is set before encoding the specific byte. TXCHARDISPVAL determines if the disparity is negative (set Low) or positive (set High). Table 2-11 illustrates this. www.xilinx.com RocketIO™ Transceiver User Guide UG024 (v3.0) February 22, 2007...

  • Page 63: Txcharisk

    8B/10B encoding is enabled. If a bit is asserted High, it means that TXDATA and TXCHARISK have combined to create an invalid control (K) character. The transmission, reception, and decode of this invalid character will create unexpected RXDATA results in the RocketIO receiver, or in other transceivers. RXCHARISK, RXRUNDISP RXCHARISK and RXRUNDISP are dual-purpose ports for the receiver depending whether 8B/10B decoding is enabled.

  • Page 64: Rxdisperr

    0 1 0 0 10111100 K28.5+ (or K28.5-) 0 1 0 1 10111100 K28.5+ (or K28.5-) 0 1 0 0 10111100 K28.5- (or K28.5+) 0 1 0 1 10111100 K28.5- (or K28.5+) www.xilinx.com RocketIO™ Transceiver User Guide UG024 (v3.0) February 22, 2007...

  • Page 65: Receiving Vitesse Channel Bonding Sequence

    Product Not Recommended for New Designs 8B/10B Encoding/Decoding The RocketIO core receives this data, but for cases where TXCHARDISPVAL is set High during data transmission, the disp_err bit in CHAN_BOND_SEQ must also be set High. Receiving Vitesse Channel Bonding Sequence On the RX side, the definition of the channel bonding sequence uses the disp_err bit to specify the flipped disparity.

  • Page 66: 8B/10B Serial Output Format

    8-bit data bus. Please use the Architecture Wizard to create instantiation templates. This wizard creates code and instantiation templates that define the attributes for a specific application. www.xilinx.com RocketIO™ Transceiver User Guide UG024 (v3.0) February 22, 2007...

  • Page 67: Serdes Alignment

    Deserializer The RocketIO transceiver core accepts serial differential data on its RXP and RXN inputs. The clock/data recovery circuit extracts clock phase and frequency from the incoming data stream and re-times incoming data to this clock. The recovered clock is presented on output RXRECCLK at 1/20 of the received serial data rate.

  • Page 68: Enpcommaalign, Enmcommaalign

    For GT_X0Y0 (bottom edge), the best slices are SLICE_X14Y0 and SLICE_X14Y1. This must be done for each MGT. Figure 2-17 shows this recommendation. GT_std_ PCOMMA_CONTROL ENPCOMMAALIGN RXRECCLK MCOMMA_CONTROL ENMCOMMAALIGN UG024_39_013103 Figure 2-17: Synchronizing Comma Align Signals to RXRECCLK www.xilinx.com RocketIO™ Transceiver User Guide UG024 (v3.0) February 22, 2007...

  • Page 69: Rocketio™ Transceiver User Guide Www.xilinx.com

    Figure 2-19 show floorplanner layouts for the two examples given above. ug024_43_031303 Figure 2-18: Top MGT Comma Control Flip-Flop Ideal Locations ug024_44_031303 Figure 2-19: Bottom MGT Comma Control Flip-Flop Ideal Locations RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v3.0) February 22, 2007...

  • Page 70: Pcomma_Detect

    COMMA_10B_MASK, PCOMMA_10B_VALUE, MCOMMA_10B_VALUE The RocketIO transceiver allows the user to define a comma character using these three attributes. The COMMA_10B_MASK bits are used in conjunction with PCOMMA_10B_VALUE (to define a plus-comma) or MCOMMA_10B_VALUE (to define a minus-comma) to define some number of recognized comma characters. High bits in the mask condition the corresponding bits in PCOMMA_10B_VALUE or MCOMMA_10B_VALUE to matter, while Low bits in the mask function as a “don’t care”...

  • Page 71: Dec_Pcomma_Detect

    RXUSRCLK and RXUSRCLK2 have different frequencies (1:2), and each edge of the slower clock is aligned to a falling edge of the faster clock. The same relationships apply to TXUSRCLK and TXUSRCLK2. See Table 2-5, page 43, for details. RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v3.0) February 22, 2007...

  • Page 72: Clock And Data Recovery

    If the byte sequence length is greater than one, and if attribute CLK_COR_REPEAT_WAIT is 0, then the transceiver can repeat the same sequence multiple times until the buffer is refilled to the half-full condition. www.xilinx.com RocketIO™ Transceiver User Guide UG024 (v3.0) February 22, 2007...

  • Page 73: Ports And Attributes

    If set to FALSE, clock correction is disabled. When clock correction is disabled, RXRECCLK must drive the receive logic in the fabric. Otherwise, the elastic buffer may over/underflow. RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v3.0) February 22, 2007...

  • Page 74: Rx_Buffer_Use

    Character CHARISK 10-Bit Data Mode (hex) CLK_COR_SEQ 8-Bit Data Mode (8B/10B Bypass) CLK_COR_SEQ_1_1 K28.5 00110111100 10011111010 CLK_COR_SEQ_1_2 D21.4 00010010101 11010100010 Β5 CLK_COR_SEQ_1_3 D21.5 00010110101 11010101010 Β5 CLK_COR_SEQ_1_4 D21.5 00010110101 11010101010 www.xilinx.com RocketIO™ Transceiver User Guide UG024 (v3.0) February 22, 2007...

  • Page 75: Clk_Cor_Seq_Len

    This attribute specifies the minimum number of RXUSRCLK cycles without clock correction that must occur between successive clock corrections. For example, if this attribute is 3, then at least three RXUSRCLK cycles without RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v3.0) February 22, 2007...

  • Page 76: Synchronization Logic

    Elastic buffer skipped one clock correction sequence for current RXDATA Elastic buffer skipped two clock correction sequence for current RXDATA Elastic buffer skipped three clock correction sequence for current RXDATA www.xilinx.com RocketIO™ Transceiver User Guide UG024 (v3.0) February 22, 2007...

  • Page 77: Rx_Los_Invalid_Incr Rx_Los_Threshold

    If RX_LOSS_OF_SYNC_FSM = TRUE, then the two bits of RXLOSSOFSYNC reflect the state of the RXLOSSOFSYNC FSM. The state machine diagram in Figure 2-21 and the three subsections following describe the three states of the RXLOSSOFSYNC FSM RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v3.0) February 22, 2007...

  • Page 78: Rx_Los_Threshold

    SYNC_ACQUIRED, unless an invalid symbol is received, in which case the FSM goes to state LOSS_OF_SYNC. LOSS_OF_SYNC (RXLOSSOFSYNC = 10) The FSM remains in this state until a comma is received, at which time it goes to state RESYNC. www.xilinx.com RocketIO™ Transceiver User Guide UG024 (v3.0) February 22, 2007...

  • Page 79: Channel Bonding (Channel Alignment)

    Master transceiver must also control the clock correction operations described in the previous section for all channel-bonded transceivers. RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v3.0) February 22, 2007...

  • Page 80: Channel Bonding (Alignment) Operation

    CHAN_BOND_WAIT = 8 CHAN_BOND_OFFSET = CHAN_BOND_WAIT CHAN_BOND_LIMIT = 2 x CHAN_BOND_WAIT Lower values are not recommended. Use higher values only if channel bonding sequences are farther apart than 17 bytes. www.xilinx.com RocketIO™ Transceiver User Guide UG024 (v3.0) February 22, 2007...

  • Page 81: Ports And Attributes

    GT_CUSTOM is the only primitive allowing modification to the sequence. These sequences are comprised of one or two sequences of length up to 4 bytes each, as set by CHAN_BOND_SEQ_LEN and CHAN_BOND_SEQ_2_USE. RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v3.0) February 22, 2007...

  • Page 82: Chan_Bond_Wait

    CHAN_BOND_LIMIT defines the expiration time after which the Slave will invalidate the most recently seen CBS location in the RX buffer. For proper alignment, this value must always be set to two times CHAN_BOND_WAIT. www.xilinx.com RocketIO™ Transceiver User Guide UG024 (v3.0) February 22, 2007...

  • Page 83: Chbonddone

    Master CBS lags the slave by too much. In this case, the slave’s CBS sequence has exceeded CHAN_BOND_LIMIT and has expired. • CBS sequences appear more frequently than CHAN_BOND_LIMIT allows, causing the Slave to align to a CBS before or after the expected one. RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v3.0) February 22, 2007...

  • Page 84: Crc (Cyclic Redundancy Check)

    CRC (Cyclic Redundancy Check) Overview Cyclic Redundancy Check (CRC) is a procedure to detect errors in the received data. The RocketIO transceiver CRC logic supports the 32-bit invariant CRC calculation used by Infiniband, Fibre Channel, and Gigabit Ethernet. CRC Operation On the transmitter side, the CRC logic recognizes where the CRC bytes should be inserted and replaces four placeholder bytes at the tail of a data packet with the computed CRC.

  • Page 85: Crc Latency

    To check the CRC error detection logic in a testing mode such as serial loopback, a CRC error can be forced by setting TXFORCECRCERR to High, which incorporates an error into the transmitted data. When that data is received, it appears “corrupted,” and the receiver RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v3.0) February 22, 2007...
  • Page 86 /K28.5/D10.4/.) Never generate the EOP frame delimiter for a beginning RD that is positive. (These are the frame delimiters that begin with /K28.5/D21.5/ or /K28.5/D10.5/.) When the RocketIO CRC determines that the running disparity must be inverted to satisfy Fibre Channel requirements, it will convert the second byte of the EOP frame delimiter (D21.4 or D10.4) to the value required to invert the running disparity...
  • Page 87 Figure 2-25: Ethernet Mode Designs should generate only the /K28.5/D16.2/ IDLE sequence for transmission, never /K28.5/D5.6/. When the RocketIO CRC determines that the running disparity must be inverted to satisfy Gigabit Ethernet requirements, it will convert the first /K28.5/D16.2/ IDLE following a packet to /K28.5/D5.6/, performing the necessary conversion.

  • Page 88: Crc_Start_Of_Packet

    RXDATA. This signals that the CRC circuitry has identified the SOF and the EOF. If a CRC error occurred, RXCRCERR will be asserted at the same time that RXCHECKINGCRC goes High. www.xilinx.com RocketIO™ Transceiver User Guide UG024 (v3.0) February 22, 2007...

  • Page 89: Txforcecrcerr, Tx_Crc_Force_Value

    This should cause the receiver to register that a CRC error has occurred. RocketIO CRC Support Limitations There are limitations to the CRC support provided by the RocketIO transceiver core: • RocketIO CRC support is implementable for single-channel use only. Computation and byte-striping of CRC across multiple bonded channels is not supported.

  • Page 90: Ports And Attributes

    FALSE. When set to TRUE, the MGT serial data will run at 10 times the reference clock rate, producing a speed range of 600 Mb/s to 1 Gb/s. www.xilinx.com RocketIO™ Transceiver User Guide UG024 (v3.0) February 22, 2007...

  • Page 91: Termination_Imp

    An important point to note is that the feedback path is at the output pads of the transmitter. This tests the entirety of the transmitter and receiver. RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v3.0) February 22, 2007...
  • Page 92 (if applicable), or simply use 50Ω resistors on the transmitter backplane pins. • Connect the unterminated TXP/TXN to the RXP/RXN of another instantiated transceiver, allowing its receiver inputs to terminate the transmitter outputs. www.xilinx.com RocketIO™ Transceiver User Guide UG024 (v3.0) February 22, 2007...

  • Page 93: Other Important Design Notes

    Other Important Design Notes Receive Data Path 32-bit Alignment The RocketIO transceiver uses the attribute ALIGN_COMMA_MSB to align protocol delimiters with the use of comma characters (special K-characters K28.5, K28.1, and K28.7 for most protocols). Setting ALIGN_COMMA_MSB to TRUE/FALSE determines where the comma characters appear on the RXDATA bus.
  • Page 94 RXRUNDISP in order to keep them properly synchronized with RXDATA. It is not possible to adjust RXCLKCORCNT appropriately for shifted/delayed RXDATA, because RXCLKCORCNT is summary data, and the summary for the shifted case cannot be recalculated. www.xilinx.com RocketIO™ Transceiver User Guide UG024 (v3.0) February 22, 2007...

  • Page 95: Bit Alignment Design

    // aligned_data[31:0] -- Properly aligned 32-bit ALIGNED_DATA // sync -- Indicator that aligned_data is properly aligned // aligned_rxisk[3:0] - properly aligned 4 bit RXCHARISK // Inputs - These are all RocketIO inputs or outputs // as indicated: // usrclk2 -- RXUSRCLK2...
  • Page 96 @ ( posedge usrclk2 ) begin if ( rxreset ) begin wait_to_sync <= 4'b1111; count <= 1'b0; else if ( rxrealign ) begin wait_to_sync <= 4'b1111; count <= 1'b1; www.xilinx.com RocketIO™ Transceiver User Guide UG024 (v3.0) February 22, 2007...
  • Page 97 <= rxdata[15:0]; rxisk_reg[1:0] <= rxisk[1:0]; if ( rxchariscomma3 ) begin aligned_data[31:0] <= rxdata[31:0]; aligned_rxisk[3:0] <= rxisk[3:0]; byte_sync <= 1'b0; else if ( rxchariscomma1 | byte_sync ) begin RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v3.0) February 22, 2007...

  • Page 98: Vhdl

    -- aligned_data[31:0] -- Properly aligned 32-std_logic ALIGNED_DATA -- sync -- Indicator that aligned_data is properly aligned -- aligned_rxisk[3:0] -properly aligned 4-std_logic RXCHARISK -- Inputs - These are all RocketIO inputs or outputs -- as indicated: www.xilinx.com RocketIO™ Transceiver User Guide...
  • Page 99 -- whenever the elastic buffer is reinitialized; -- that is, upon asserted RXRESET or -- RXREALIGN. Count-down is enabled whenever a -- comma is known to have -- come through the comma detection circuit, that RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v3.0) February 22, 2007...
  • Page 100 -- assuming that incoming commas are aligned -- to [31:24] or [15:8]. -- Here, you could add code to use ENPCOMMAALIGN and -- ENMCOMMAALIGN to enable a move back into the www.xilinx.com RocketIO™ Transceiver User Guide UG024 (v3.0) February 22, 2007...
  • Page 101 DOWNTO 2); byte_sync <= '1'; ELSE rxdata_hold(31 DOWNTO 0) <= rxdata(31 DOWNTO 0); rxisk_hold(3 DOWNTO 0) <= rxisk(3 DOWNTO 0); END IF; END IF; END IF; END PROCESS; END ARCHITECTURE translated; RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v3.0) February 22, 2007...
  • Page 102 Product Not Recommended for New Designs Chapter 2: Digital Design Considerations www.xilinx.com RocketIO™ Transceiver User Guide UG024 (v3.0) February 22, 2007...

  • Page 103: Serial I/O Description

    TXN pin GNDA UG024_46_021704 Figure 3-1: Differential Amplifier The RocketIO transceiver is implemented in Current Mode Logic (CML). A CML output consists of transistors configured as shown in Figure 3-1. CML uses a positive supply and offers easy interface requirements. In this configuration, both legs of the driver, V and V sink current, with one leg always sinking more current than its complement.

  • Page 104: Pre-Emphasis Techniques

    LOGIC or normal level (i.e., no pre-emphasis). A second characteristic of RocketIO transceiver pre-emphasis is that the STRONG level is reduced after some time to the LOGIC level, thereby minimizing the voltage swing necessary to switch the differential pair into the opposite state.

  • Page 105: Rocketio™ Transceiver User Guide Www.xilinx.com

    Product Not Recommended for New Designs Pre-emphasis Techniques UG024_17_020802 Figure 3-2: Alternating K28.5+ with No Pre-Emphasis Logic High Strong High Logic Low Strong Low UG024_18_020802 Figure 3-3: K28.5+ with Pre-Emphasis RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v3.0) February 22, 2007...
  • Page 106 Product Not Recommended for New Designs Chapter 3: Analog Design Considerations ug024_36_031803 Figure 3-4: Eye Diagram, 10% Pre-Emphasis, 20" FR4, Worst-Case Conditions ug024_37_031803 Figure 3-5: Eye Diagram, 33% Pre-Emphasis, 20" FR4, Worst-Case Conditions www.xilinx.com RocketIO™ Transceiver User Guide UG024 (v3.0) February 22, 2007...

  • Page 107: Differential Receiver

    (ITU). Jitter is typically expressed in a decimal fraction of Unit Interval (UI), e.g. 0.3 UI. Total Jitter = Deterministic Jitter (DJ) + Random Jitter (RJ). RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v3.0) February 22, 2007...

  • Page 108: Clock And Data Recovery

    The serial transceiver input is locked to the input data stream through Clock and Data Recovery (CDR), a built-in feature of the RocketIO transceiver. CDR keys off the rising and falling edges of incoming data and derives a clock that is representative of the incoming data rate.

  • Page 109: Pcb Design Requirements

    Xilinx, Inc. Power Conditioning Each RocketIO transceiver has five power supply pins, all of which are sensitive to noise. Table 3-5 summarizes the power supply pins, their names, and associated voltages. For power and current requirements of each supply, refer to the data sheet (DS083).

  • Page 110: Termination Voltage

    Vendor application examples typically recommend a 10 μF capacitor on the input and a 10 μF capacitor on the output of the regulator. For use with RocketIO transceivers, Xilinx requires that this be modified according to the capacitor topology shown in Figure 3-7.

  • Page 111: Passive Filtering

    PCB Design Requirements with a transceiver from another vendor, termination voltage can be dictated by the specifications of the other transceiver. In cases where the RocketIO transceiver is interfacing with another RocketIO transceiver, any termination voltage can be used. With AVCCAUXTX and AVCCAUXRX already powered with 2.5V, an obvious choice for VTTX...
  • Page 112 “External” denote a device for which the user must provide power filtering capacitors externally on the PCB; those labeled “Internal” denote a device that contains all necessary 0.22 μF capacitors for RocketIO power pins. Table boxes that say “No MGTs” denote a device that does not have any RocketIO transceivers.
  • Page 113 PCB layer, with lands for the capacitors and ferrite beads of the AVCCAUXTX and AVCCAUXRX supplies. The ferrite beads are mounted at the eight “L[n]” locations; the capacitors are mounted at the eight “C[n]” locations. RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v3.0) February 22, 2007...
  • Page 114 Product Not Recommended for New Designs Chapter 3: Analog Design Considerations Figure 3-10: Example Power Filtering PCB Layout for Four MGTs, In Device with External Capacitors, Top Layer www.xilinx.com RocketIO™ Transceiver User Guide UG024 (v3.0) February 22, 2007...

  • Page 115: High-Speed Serial Trace Design

    High-Speed Serial Trace Design Routing Serial Traces All RocketIO transceiver I/Os are placed on the periphery of the BGA package to facilitate routing and inspection (since JTAG is not available on serial I/O pins). Two output/input impedance options are available in the RocketIO transceivers: 50Ω and 75Ω. Controlled impedance traces with a corresponding impedance should be used to connect the RocketIO transceiver to other compatible transceivers.

  • Page 116: Differential Trace Design

    PCB routes carry especially noisy signals, such as TTL and other similarly noisy standards. The RocketIO transceiver is designed to function at 3.125 Gb/s through 40 inches of PCB with two high-bandwidth connectors. Longer trace lengths require either a low-loss dielectric or considerably wider serial traces.

  • Page 117: Ac And Dc Coupling

    = 100Ω Differential UG024_23_042503 Figure 3-15: AC-Coupled Serial Link DC coupling (direct connection) is preferable in cases where RocketIO transceivers are interfaced with other RocketIO transceivers or other Mindspeed transceivers that have compatible differential and common mode voltage specifications. Passive components are not required when DC coupling is used.
  • Page 118 UG024_24_042503 Figure 3-16: DC-Coupled Serial Link The RocketIO differential receiver produces the best bit-error rates when its common- mode voltage falls between 1.6V and 1.8V. When the receiver is AC-coupled to the line, is the sole determinant of the receiver common-mode voltage, and therefore must be set to a value within this range.

  • Page 119: Reference Clock

    Figure 3-20. LV1145B LVDS 100Ω 2.5V-LVDS UG024_025b_050102 Figure 3-19: LVDS Reference Clock Oscillator Interface LV1145B LVDS_25_DT 2.5V-LVDS 100Ω UG024_025d_071504 Figure 3-20: LVDS Reference Clock Oscillator Interface (On-Chip Termination) RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v3.0) February 22, 2007...

  • Page 120: Powering The Rocketio Transceivers

    Other Important Design Notes Powering the RocketIO Transceivers IMPORTANT! All RocketIO transceivers in the FPGA, whether instantiated in the design or not, must be connected to power and ground. Unused transceivers may be powered by any 2.5 V source, and passive filtering is not required.

  • Page 121: Simulation Models

    HSPICE HSPICE is an analog design model that allows simulation of the RX and TX high-speed transceiver. To obtain these HSPICE models, go to the Xilinx Download Center at: http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp. Select HSPICE and Eldo Models and then Virtex-II Pro from the pull-down menus.
  • Page 122 Bottom of device CHBONDO CHBONDI CHBONDO CHBONDI CHBONDO CHBONDI CHBONDO CHBONDI CHBONDO CHBONDI CHBONDO CHBONDI CHBONDO CHBONDI CHBONDO CHBONDI SLAVE_2_HOPS SLAVE_2_HOPS SLAVE_2_HOPS SLAVE_1_HOP SLAVE_2_HOPS SLAVE_2_HOPS SLAVE_2_HOPS SLAVE_2_HOPS UG024_08_020802 Figure 4-2: XC2VP50 Implementation www.xilinx.com RocketIO™ Transceiver User Guide UG024 (v3.0) February 22, 2007...

  • Page 123: Mgt Package Pins

    AB15, AB16 AF10, AF9 GT_X2_Y1 A13, A14, A12, A11, A15, A16 A10, A9 GT_X3_Y0 AB17, AB18, AF7, AF6, AB19, AB20 AF5, AF4 GT_X3_Y1 A17, A18, A7, A6, A5, A19, A20 RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v3.0) February 22, 2007...
  • Page 124 GT_X5_Y1 A5, A4, A3, A13, A12, A11, A10 GT_X6_Y0 AP9, AP8, AP7, AP6 GT_X6_Y1 A9, A8, A7, GT_X7_Y0 AP5, AP4, AP3, AP2 GT_X7_Y1 A5, A4, A3, GT_X8_Y0 GT_X8_Y1 GT_X9_Y0 GT_X9_Y1 www.xilinx.com RocketIO™ Transceiver User Guide UG024 (v3.0) February 22, 2007...
  • Page 125 BB9, BB8, BB7, BB6 GT_X8_Y1 A9, A8, A7, A6 GT_X9_Y0 AW7, AW6, AW5, BB5, BB4, BB3, BB2 GT_X9_Y1 A7, A6, A5, A4 A5, A4, A3, A2 GT_X10_Y0 GT_X10_Y1 GT_X11_Y0 GT_X11_Y1 RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v3.0) February 22, 2007...
  • Page 126 Product Not Recommended for New Designs Chapter 4: Simulation and Implementation www.xilinx.com RocketIO™ Transceiver User Guide UG024 (v3.0) February 22, 2007...
  • Page 127 RocketIO core logic are ignored. Signals are characterized with setup and hold times for inputs, and with clock to valid output times for outputs. There are five clocks associated with the RocketIO core, but only three of these clocks— RXUSRCLK, RXUSRCLK2, and TXUSRCLK2—have I/Os that are synchronous to them.
  • Page 128 Product Not Recommended for New Designs Appendix A: RocketIO Transceiver Timing Model PACKAGE PINS MULTI-GIGABIT TRANSCEIVER CORE FPGA FABRIC AVCCAUXRX Power Down 2.5V RX POWERDOWN RXRECCLK VTRX Termination Supply RX RXPOLARITY RXREALIGN RXCOMMADET ENPCOMMAALIGN ENMCOMMAALIGN RXCHECKINGCRC Check RXCRCERR RXDATA[15:0] RXDATA[31:16]...

  • Page 129: Timing Parameters

    Setup/Hold Times of Inputs Relative to Clock Basic Format: ParameterName_SIGNAL where ParameterName = T with subscript string defining the timing relationship SIGNAL name of RocketIO signal synchronous to the clock ParameterName Format: Setup time before clock edge GxCK Hold time after clock edge GCKx where...

  • Page 130: Clock Pulse Width

    The following four tables list the timing parameters as reported by the implementation tools relative to the clocks given in Table A-1, along with the RocketIO signals that are synchronous to each clock. (No signals are synchronous to REFCLK or TXUSRCLK.) A timing diagram (Figure A-2) illustrates the timing relationships.
  • Page 131 GCCK GCKC _TCRCE/T _TCRCE Control inputs TXFORCECRCERR GCCK GCKC _TPOL/T _TPOL Control inputs TXPOLARITY GCCK GCKC _TINH/T _TINH Control inputs TXINHIBIT GCCK GCKC _LBK/T _LBK Control inputs LOOPBACK[1:0] GCCK GCKC RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v3.0) February 22, 2007...
  • Page 132 Clock pulse width, Low state TXUSRCLK TX2PWL Notes: 1. REFCLK is not synchronous to any RocketIO signals. 2. BREFCLK is not synchronous to any RocketIO signals. 3. TXUSRCLK is not synchronous to any RocketIO signals. www.xilinx.com RocketIO™ Transceiver User Guide...
  • Page 133 Timing Parameter Tables and Diagram x GWL x GWH CLOCK GCCK GCKC CONTROL INPUTS GCKCO CONTROL OUTPUTS GCKDO DATA OUTPUTS GDCK GCKD DATA INPUTS UG012_106_02_100101 Figure A-2: RocketIO Transceiver Timing Relative to Clock Edge RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v3.0) February 22, 2007...
  • Page 134 Product Not Recommended for New Designs Appendix A: RocketIO Transceiver Timing Model www.xilinx.com RocketIO™ Transceiver User Guide UG024 (v3.0) February 22, 2007...

  • Page 135: Valid Data Characters

    011100 0100 D15.0 000 01111 010111 0100 101000 1011 D16.0 000 10000 011011 0100 100100 1011 D17.0 000 10001 100011 1011 100011 0100 D18.0 000 10010 010011 1011 010011 0100 RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v3.0) February 22, 2007...
  • Page 136 101100 1001 D14.1 001 01110 011100 1001 011100 1001 D15.1 001 01111 010111 1001 101000 1001 D16.1 001 10000 011011 1001 100100 1001 D17.1 001 10001 100011 1001 100011 1001 www.xilinx.com RocketIO™ Transceiver User Guide UG024 (v3.0) February 22, 2007...
  • Page 137 001101 0101 D13.2 010 01101 101100 0101 101100 0101 D14.2 010 01110 011100 0101 011100 0101 D15.2 010 01111 010111 0101 101000 0101 D16.2 010 10000 011011 0101 100100 0101 RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v3.0) February 22, 2007...
  • Page 138 110100 0011 D12.3 011 01100 001101 1100 001101 0011 D13.3 011 01101 101100 1100 101100 0011 D14.3 011 01110 011100 1100 011100 0011 D15.3 011 01111 010111 0011 101000 1100 www.xilinx.com RocketIO™ Transceiver User Guide UG024 (v3.0) February 22, 2007...
  • Page 139 001101 0010 D13.4 100 01101 101100 1101 101100 0010 D14.4 100 01110 011100 1101 011100 0010 D15.4 100 01111 010111 0010 101000 1101 D16.4 100 10000 011011 0010 100100 1101 RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v3.0) February 22, 2007...
  • Page 140 101100 1010 D14.5 101 01110 011100 1010 011100 1010 D15.5 101 01111 010111 1010 101000 1010 D16.5 101 10000 011011 1010 100100 1010 D17.5 101 10001 100011 1010 100011 1010 www.xilinx.com RocketIO™ Transceiver User Guide UG024 (v3.0) February 22, 2007...
  • Page 141 011100 0110 D15.6 110 01111 010111 0110 101000 0110 D16.6 110 10000 011011 0110 100100 0110 D17.6 110 10001 100011 0110 100011 0110 D18.6 110 10010 010011 0110 010011 0110 RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v3.0) February 22, 2007...
  • Page 142 101000 1110 D16.7 111 10000 011011 0001 100100 1110 D17.7 111 10001 100011 0111 100011 0001 D18.7 111 10010 010011 0111 010011 0001 D19.7 111 10011 110010 1110 110010 0001 www.xilinx.com RocketIO™ Transceiver User Guide UG024 (v3.0) February 22, 2007...

  • Page 143: Valid Control Characters (K-Characters)

    110110 1000 001001 0111 K29.7 111 11101 101110 1000 010001 0111 K30.7 111 11110 011110 1000 100001 0111 Notes: 1. Used for testing and characterization only. Do not use in protocols. RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v3.0) February 22, 2007...
  • Page 144 Product Not Recommended for New Designs Appendix B: 8B/10B Valid Characters www.xilinx.com RocketIO™ Transceiver User Guide UG024 (v3.0) February 22, 2007...

  • Page 145: Application Notes

    This module can be used with the Virtex-II Pro™ RocketIO™ Multi-Gigabit Transceiver (MGT) to achieve line rates of 200 Mb/s to 1000 Mb/s. When using the Virtex-II Pro RocketIO MGT, sinusoidal input jitter tolerance exceeds 0.55 UI(1) for 3/4/5X oversampling when tested with the PRBS-23 data pattern, and over 0.38 UI(2) when tested with the SONET CID data pattern.

  • Page 146: Xapp649: Sonet Rate Conversion In Virtex-Ii Pro Devices

    2.5 Gb/s. At a 156.25 MHz input, the output is at its maximum speed of 3.125 Gb/s. The parallel data stream applied to the RocketIO transceiver can either be 20 bits direct, or it can be written as 16 bits, to which 8b/10b coding is applied to generate the 20 bits required.

  • Page 147: Xapp661: Rocketio Transceiver Bit-Error Rate Tester

    Virtex-II Pro design already utilizing the PLB or OPB bus structures. The reference design uses a Xilinx intellectual property interface (IPIF) connecting to either the PLB or OPB buses. This design also provides for a terminal interface using a serial port connection, allowing MGT attribute settings to be changed through command line entries.

  • Page 148: Rocketio Transceiver

    Virtex-II Pro™ RocketIO™ transceiver. This note is only applicable for designs that do not use the clock correction or channel bonding features of the RocketIO transceiver. (These operations can still be done in the fabric, if needed).

  • Page 149: Multi-Gigabit Transceivers

    Virtex-II Pro devices makes it possible to implement multi-rate SDI interfaces. Since all Virtex-II Pro devices have four or more RocketIO transceivers, it is possible to implement multiple HD-SDI and SDI-SDI interfaces in a single FPGA.

  • Page 150: Characterization Summary

    Each MGT has separate transmit and receive functions (full-duplex) and can be operated at baud rates from 600 Mb/s to 3.125 Gb/s. Additionally, every RocketIO MGT block is fully independent and contains a complete set of common SerDes (serializer/deserializer) functions. This allows Virtex-II Pro devices to...

  • Page 151: Embedded Rocketio Transceivers

    CX27201. The features offered by each of these devices are presented, along with a discussion of how the RocketIO transceiver can afford an alternative to each multi-chip solution. Links to Xilinx information resources for the Virtex-II Pro Platform FPGA and embedded RocketIO transceiver are presented in the final section.
  • Page 152 Product Not Recommended for New Designs Appendix C: Related Online Documents www.xilinx.com RocketIO™ Transceiver User Guide UG024 (v3.0) February 22, 2007...

  • Page 153: Index

    Clock Correction (Recovery) 1-byte clock DEC_MCOMMA_DETECT clock recovery 2-byte clock DEC_PCOMMA_DETECT overview 32-bit alignment design DEC_VALID_COMMA_ONLY ports and attributes 4-byte clock MCOMMA_10B_VALUE Clock/Data Recovery (CDR) parameters VHDL MCOMMA_DETECT 1-byte clock RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v3.0) February 22, 2007...
  • Page 154 Clock clock correction Simulation Models SmartModels SERDES alignment Random Jitter (RJ) Synchronization Logic synchronization logic Receive Data Path 32-bit Alignment overview Ports (defined) Receiver Buffer ports and attributes www.xilinx.com RocketIO™ Transceiver User Guide UG024 (v3.0) February 22, 2007...
  • Page 155 Total Jitter (DJ + RJ) Transmitter and Elastic (Receiver) Buffers Transmitter Buffer (FIFO) User Guide conventions online references port and attribute names typographical Vitesse Disparity Example Voltage Regulator Selection and Use RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v3.0) February 22, 2007...
  • Page 156 Product Not Recommended for New Designs www.xilinx.com RocketIO™ Transceiver User Guide UG024 (v3.0) February 22, 2007...

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