Appendix C: Dynamic Reconfiguration Port; Interface Description - Xilinx Virtex-4 RocketIO User Manual

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Dynamic Reconfiguration Port
The Virtex®-4 RocketIO™ transceivers provide a simple parallel-programming port for
dynamically configuring the PMA and PCS attribute settings. This gives the user real-time
control of all transceiver features without the need to use partial reconfiguration or to
bring out discrete control ports to the fabric for each attribute. This configuration port is
identical to the Dynamic Reconfiguration Port (DRP) for other Virtex-4 primitives, such as
the DCM and system monitor.
For more details of this interface, see the Virtex-4 Configuration Guide (UG071).
Note:
1.
2.
3.
4.

Interface Description

The Dynamic Reconfiguration Port consists of a simple, 2-byte-wide interface. The user
accessible ports are defined in
Table C-1: Dynamic Reconfiguration Port Ports
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
This feature is intended for advanced users only. Direct modification of these attributes
should only be done with a thorough understanding of the capabilities, performance,
and side-effects of the resulting settings. For most applications, the default attribute
settings provided in the software primitives should be adequate.
Improper settings can cause excessive power consumption.
Because modification of some registers can affect the PLL performance during
reconfiguration, reconfiguration time can run anywhere between 10 µs and 10 ms,
approximately.
Attempts to address DRP locations outside the defined memory map can fail to return
a DRDY. User logic should provide safeguards against this condition by mechanisms
such as a time-out or similar.
Port I/O Size
DADDR I 8
DCLK I 1
DEN I 1
DI I 16
DO O 16
DRDY O 1
DWE I 1
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Table C-1. The DRP is not affected by PMARESET.
Definition
Dynamic reconfiguration address bus
Dynamic Reconfiguration Port clock
Dynamic Reconfiguration Port enable when set to a logic 1
Dynamic reconfiguration input data bus
Dynamic reconfiguration output data bus
Strobe that indicates read/write cycle is complete
Dynamic reconfiguration write enable when set to a logic 1
Appendix C
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