Timing; Usage - Xilinx Virtex-4 RocketIO User Manual

Chapter 8: Low-Latency Design
synchronous clock divider setting (32-bit or 40-bit data path). The circuit adjusts one high-
speed clock for every parallel clock being used as the timing reference (GREFCLK or PCS
TXCLK). The synchronization clock frequency can be equal to or slower than PMA
TXCLK0.
The phase alignment process should be initiated only after the TX PLL is locked, as
indicated by the TXLOCK output. If for any reason the TX PLL becomes unlocked, the
alignment process must be re-executed to insure the output skew is correct.

Timing

Figure 8-15
alignment process.
GREFCLK or

Usage

1.
2.
3.
214
illustrates the timing waveform of all the signals involved in the TX phase
PCS TXCLK
TXCLK0
TXLOCK
TXSYNC
TXRESET
Note: PCS TXCLK and TXCLK0 are MGT internal signals, not MGT fabric ports.
Phase alignment is a one-time, multi-clock-cycle event enabled when the TXSYNC
port is asserted. Although the TXSYNC port is asynchronous to TXUSRCLK2, the user
can simply generate TXSYNC in the TXUSRCLK2 domain and apply the TXSYNC
signal to all MGTs involved in the TX phase alignment.
TX phase alignment should not be initiated until all involved TX PLLs are locked.
Refer to "Resets" in Chapter 2
example, FDET_LCK_SEL and TXLOOPFILT), the required TXLOCK-to-TXSYNC
interval (TLOCK_to_SYNC) can vary greatly, from a few TXUSRCLK2 cycles to
several thousand TXUSRCLK2 cycles.
a. It is recommended that TXSYNC be asserted after TXLOCK has remained High for
at least 12,000 TXUSRCLK2 cycles.
b. This TXLOCK-to-TXSYNC interval can be reduced when using a different
FDET_LCK_SEL setting.
The TXSYNC port must remain asserted for the entire phase alignment process.
a. TXSYNC must be asserted for least 64 synchronization clock cycles (TSYNC).
b. The synchronization clock (alignment reference) can be GREFCLK or PCS TXCLK.
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Phase Alignment in
Progress
T
LOCK to SYNC
Figure 8-15: TXSYNC Timing
for more details. Depending on the TX PLL settings (for
T
T
SYNC
SYNC_to_RST
T
RST
UG076_ch8_11_041106
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
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