Use Models - Xilinx Virtex-4 RocketIO User Manual

Chapter 8: Low-Latency Design

Use Models

Table 8-11: RX Use Models: Low-Latency Buffered Mode
RX_1A
Internal PCS clock
dividers to derive
RXUSRCLK from
TRUE
RXUSRCLK2
RX_1B
External RXUSRCLK
RX_1C
Notes:
1. All cases addressed assume a 4-byte fabric width.
2. All cases addressed use external RXUSRCLK. To use the internal PCS dividers, refer to section
the internal PCS dividers, only Pre-Driver Serial Loopback or Normal Operation are possible. Parallel Loopback is not supported.
3. 64B/66B encoding/decoding is not supported.
220
No Bypass. Uses
10GBASE-R Decode
and 64B/66B
Descrambler and
Block Sync.
No Bypass. Uses
OR 8B/10B Decode.
Decoding Bypass of
8B/10B and 64B/66B
Decode.
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PORTS
1 1 0 1 1
NOT
USED
Tie to
0 1 1 0 0
logic 0
0 1 0 0 0
"Clocking," page
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
R
ATTRIBUTES
00 00
FALSE FALSE
00 00
00 00
219. When using