16-Bit Transmission, Hold Crc, And Residue Of 8-Bit Example - Xilinx Virtex-4 RocketIO User Manual

Chapter 5: Cyclic Redundancy Check (CRC)

16-Bit Transmission, Hold CRC, and Residue of 8-Bit Example

In this example
value is shown. This example also illustrates a different residue data width. Notice that the
internal data is used when there is correct data and is don't care otherwise. The internal
CRC is the same for two consecutive CRCCLK cycles. CRCOUT is updated as always
according to the interface clock. Packet length in bits must be an integer multiple of an 8-bit
word.
CRCINTCLK
CRCIN [63:32]
xx xx
xx
CRCDATAWIDTH
CRCINIT
CRCDATAVALID
CRCCLK
Internal CRCIN [31:0]
x x
Internal CRCOUT [31:0]
CRCOUT[31:0]
xx
Figure 5-5: 16-Bit Transmission, Hold CRC, and Residue of 8-Bit Example
160
(Figure 5-5), data is 16 bits wide and the method for holding the CRCOUT
(1) (2) (3) xx
16
x x 1 x 2 x 3 x
x x x x x 1 1 2 2 3
1
xx xx xx
C
Initial CRC
www.xilinx.com
xx xx (-3) (-2)
16
-3
x x x x x
3 3 3 3 3
2 3 3
C
C C
Internal Valid CRC at 32-Bit
Boundary
(-1) (n) xx xx xx
8 xx xx xx
-2 -1 n
x x x x x x x
C C C
3 -3 -3 -2 -2 -1 -1
3 -3 -2 -1 n
C
C C C C
Output CRC
UG076_03_090605
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
R
xx
xx
x x
xx