Figure 2-11 (Cont'd): Receive Clocking Decision Flow (Page 2 Of 2) - Xilinx Virtex-4 RocketIO User Manual

R
(cont'd from previous page)
NO
Provide
(7)
USRCLK?
externally?
1-byte fabric
interface
YES
YES
RX_CLOCK_DIVIDER
= 00 = 10
DONE with
RX
Settings

Figure 2-11 (Cont'd): Receive Clocking Decision Flow (Page 2 of 2)

Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
Does
RXDIGRX =
TRUE
YES
RXRECCLK1_USE_SYNC
= TRUE
64B/66B
(8)
decoding?
YES
RXCLKMODE[5:4] = 11
RXCLKMODE[2:1] = 10
NO
NO
2-byte fabric
interface
4-byte fabric
YES
interface
= 01 = 11
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NO
RXRECCLK1_USE_SYNC
= FALSE
NO
NO
8B/10B
decoding?
YES
RXCLKMODE[5:4] = 00
RXCLKMODE[2:1] = 01
NO
Is it a 1-byte fabric
(5)
interface?
NO
2-byte fabric
(5)
YES interface
YES
4-byte fabric
interface
YES
RXASYNCDIVIDE
= 00 = 01 = 10
RX_CLOCK_DIVIDER = 00
RXCLK0_FORCE_PMACLK = TRUE
Low Latency NO
(3)(4)
Mode?
YES
NO
Is RXDIGRX =
TRUE?
DIGRX_SYNC_MODE = 0
YES
DIGRX_SYNC_MODE = 1
RXCLK0_FORCE_PMACLK = FALSE
RXCLK0_FORCE_PMACLK = TRUE
Setting the Clocking Options
SONET or no
decoding
RXCLKMODE[5:4] = 10
RXCLKMODE[2:1] = 11
NO
8-byte fabric
(6)
interface
= 10
ug076_ch2_08b_072607
79