Rxslide; Clock Correction; Append/Remove Idle Clock Correction - Xilinx Virtex-4 RocketIO User Manual

R

RXSLIDE

RXSLIDE allows manual control of the PCS barrel shifter for applications that require an
alignment function that cannot be defined with PCOMMA_32B_VALUE/
MCOMMA_32B_VALUE. When RXSLIDE is set to a logic 1, the position of the barrel
shifter can be adjusted by one bit. This data increment can continue until it reaches the
most significant bit, equal to the maximum word length minus 1, where it rolls over.
•
•
Every RXSLIDE pulse causes a bit slip from a lower bit to higher bit.
RXSLIDE functionality is shown in
RXUSRCLK2
RXDATA
RXSLIDE
Notes:
1. Datapath_delay depends on what receiver functions are used.
2. The receive data is continuously 0x00000004. The data changes are caused by the rising and falling edge of RXSLIDE.
Note:
RXSLIDE should be used instead.

Clock Correction

Clock correction is needed when the rate that data is fed into the write side of the receive
buffer is either slower or faster than the rate that data is retrieved from the read side of the
receive buffer. The rate of write data entering the buffer is determined by the frequency of
RXRECCLK1/RXRECCLK2. The rate of read data retrieved from the read side of the buffer
is determined by the frequency of RXUSRCLK.

Append/Remove Idle Clock Correction

When the attribute CLK_COR_SEQ_DROP is set Low and CLK_CORRECT_USE is set
High, the Append/Remove Idle Clock Correction mode is enabled. The Append/Remove
Idle Clock Correction mode corrects for differing clock rates by finding clock correction
sequences in the bitstream, and then either appending or removing sequences at the point
where the sequences were found.
Note:
to be dropped despite the status of the buffer, and no appending to the buffer is allowed, eventually
causing the buffer to empty. CLK_COR_SEQ_DROP should ALWAYS be set to FALSE.
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
RXSLIDE must be set to logic 1 for a minimum of one RXUSRCLK2 cycle for bit slip to
occur.
RXSLIDE must be set to logic 0 for a minimum of three RXUSRCLK2 cycles before
being set to logic 1 again.
0x00000004
(1)
Datapath_delay
Figure 3-18: RXSLIDE Timing Waveform
RXSYNC with the PCS_BIT_SLIP attribute is no longer recommended for the bit slip feature.
CLK_COR_SEQ_DROP, when set to TRUE, causes all matched clock correction sequences
www.xilinx.com
Figure 3-18.
0x00000008 0x00000010
Clock Correction
0x00000020
ug076_ch3_9c_073107
123