Txreset; Rxreset - Xilinx Virtex-4 RocketIO User Manual

Chapter 2: Clocking, Timing, and Resets
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TXRESET

The TXRESET is used to bring every flip-flop in the TX PCS to a known value but does not
affect the PMA. When TXRESET is set to logic 1, the TX PCS is considered to be in reset.
Below is a list of requirements for TXRESET:
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The blocks affected by TXRESET are:
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See
While TXRESET is asserted, the transmit data going into the PMA is all 0s.

RXRESET

The RXRESET is used to bring every flip-flop in the RX PCS to a known value but does not
affect the PMA. When the signal RXRESET is set to a logic 1, the RX PCS is considered in
reset. Below is a list of requirements for RXRESET:
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The blocks affected by RXRESET are:
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84
Set RXPMARESET to logic 1 at startup for a minimum of three USRCLK cycles (based
on internal data width).
Do not use the output clocks of the MGT for clocking this reset.
Need to have stable clock on both the TXUSRCLK and PCS TXCLK domains on the
deassertion of TXRESET to obtain reliable pointer initialization of the TX buffer. (See
Figure 2-8, "PCS Transmit Clocking Domains and Datapaths," page
Set TXRESET signal to logic 1 for a minimum of three cycles of the slowest frequency
on TXUSRCLK or TXUSRCLK2.
After deassertion of TXRESET, the TX PCS takes five cycles of the slowest frequency
on TXUSRCLK or TXUSRCLK2 for each clock domain to come out of reset.
For 8-byte external data interface widths, TXRESET should be deasserted
synchronously to the falling edge of TXUSRCLK2 clock to ensure proper transmit
data ordering. See Figure
page 100.
Tx Fabric Interface — TXUSRCLK and TXUSRCLK2 domains
8B/10B Encode — TXUSRCLK domain
Tx Buffer — TXUSRCLK and PCS TXCLK domains
Figure 2-8, "PCS Transmit Clocking Domains and Datapaths," page
Need to have stable clock on both the RXUSRCLK and PCS RXCLK domains on the
deassertion of RXRESET to obtain reliable pointer initialization of the RX buffer. (See
Figure 2-7, "PCS Receive Clocking Domains and Datapaths," page
Set RXRESET signal to logic 1 for a minimum of three cycles of the slowest frequency
on RXUSRCLK or RXUSRCLK2.
After deassertion of RXRESET, the RX PCS takes five cycles of the slowest frequency
on RXUSRCLK or RXUSRCLK2 for each clock domain to come out of reset.
When channel bonding is used in conjunction with 1-byte and 2-byte external data
interface widths, RXRESET must be deasserted synchronously on all channel-bonded
MGTs with respect to RXUSRCLK2.
RX Fabric Interface — RXUSRCLK and RXUSRCLK2 domains
8B/10B Decode — RXUSRCLK domain
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2-24, "TXRESET for 8-Byte External Data Interface Width,"
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Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
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