Figure 2-21: Resetting The Receiver In Analog Cdr Mode Where Rx Buffer Is Used; Receive Reset Sequence: Rx Buffer Bypassed - Xilinx Virtex-4 RocketIO User Manual

Chapter 2: Clocking, Timing, and Resets
RXPMARESET

Figure 2-21: Resetting the Receiver in Analog CDR Mode Where RX Buffer Is Used

Receive Reset Sequence: RX Buffer Bypassed

Figure 2-22
bypassed.
Refer to the following points in conjunction with this figure.
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96
RXUSRCLK
RXLOCK
RXRESET
RXBUFERR
provides a flow chart of the receive reset sequence when the RX buffer is
The flow chart uses RXUSRCLK as reference to the wait time for each state. Do not use
RXUSRCLK as the clock source for this block; this clock might not be present during
some states. Use a free-running clock (for example, the system's clock) and make sure
that the wait time for each state equals the specified number of RXUSRCLK cycles.
It is assumed that the frequency of RXUSRCLK is slower than the frequency of
RXUSRCLK2. If RXUSRCLK2 is slower, use that clock as reference to the wait time for
each state.
See Figure 8-22, "RXSYNC Timing," page 228
cycles specified in this block.
rx_usrclk_stable is a status signal from the user's application that is asserted High
when both RXUSRCLK and RXUSRCLK2 clocks are stable. For example, if a DCM is
used to generate both the RXUSRCLK and RXUSRCLK2 clocks, then the DCM
LOCKED signal can be used here.
rx_error is a status signal from the user's application that is asserted High indicating
that there is a burst of errors on the received data (RXDISPERR and/or
RXNOTINTABLE are asserted). The errors observed in the received data also show if
an RX phase alignment has not been successful, so there is no need for a separate align
error signal from the user similar to the TX reset sequence.
rx_sync_cnt is a counter from the user's application that is incremented every time
both rx_error and RXLOCK are asserted. It is reset when the block cycles back to the
RX_PMA_RESET state.
See "RX Reset Sequence Background," page 100
cycles requirement.
This RX reset sequence is for Analog CDR mode. The RX buffer bypass mode is not
supported with the digital receiver.
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Once RX error is monitored Low for some time, RX Link is READY
regarding the 64 synchronization clock
for information on the 16K REFCLK
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
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ug076_ch2_22_040406