Rx Reset Sequence Background - Xilinx Virtex-4 RocketIO User Manual

Chapter 2: Clocking, Timing, and Resets
(based on TXUSRCLK2)
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RX Reset Sequence Background

When the MGT is used in Analog CDR Mode, its RXLOCK port is asserted after the RX
PLL locks to the reference clock. The RXLOCK signal remains High for as few as 128
REFCLK cycles with the loosest receive calibration settings (see
page
at the receiver or if the PLL is not able to lock to data, the RXLOCK signal transitions back
to Low in as few as 128 REFCLK cycles or as many as 16,384 REFCLK cycles, depending on
the receive calibration settings. The process repeats until lock-to-data is acquired. It is
recommended to wait 16K (16 x 1024) REFCLK periods for the reset sequence to ensure
that the PLL is locked to data.
Because the RX PLL is locked to the reference clock in Digital CDR mode, there is no need
to assert RXLOCK High for a specific number of REFCLK cycles.
100
TXUSRCLK
TXUSRCLK2
TXRESET
TXDATA
Internal txdata
(based on TXUSRCLK)
Figure 2-24: TXRESET for 8-Byte External Data Interface Width
For Digital CDR, asserting RXRESET causes the PMA parallel clock RXRECCLK1 to
remain at a constant value.
When channel bonding is used in conjunction with 1-byte and 2-byte external data
interface widths, RXRESET must be deasserted synchronously on all channel-bonded
MGTs with respect to RXUSRCLK2.
149). At this point, the receiver tries to lock onto incoming data. If no data is present
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ug076_ch2_26_040406
"Calibration for the PLLs,"
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
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