Pma Configurations - Xilinx Virtex-4 RocketIO User Manual

R
TXDATA (2,4,8B)

PMA Configurations

There are several configurations of the PMA that also affect serial speeds and clocking
schemes. These configurations can be modified by the Dynamic Reconfiguration Port or
with attributes. These settings are covered in
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
TX_CLOCK_DIVIDER
TXUSRCLK
÷2
÷4
TXUSRCLK2
TXUSRCLK2 TXUSRCLK
TXOUTCLK1/
TXOUTCLK2
8B/10B
Encode
10GBASE-R
TXCHARISK
(1)
Encode
ETC.
PCS
Note: (1) 64B/66B encoding/decoding is not supported.
Figure 2-8: PCS Transmit Clocking Domains and Datapaths
www.xilinx.com
PMA/PCS Clocking Domains and Data Paths
TXCLK0_FORCE_PMACLK,
TX_CLOCK_DIVIDER
00
10 01 11
010 001
PCS
TXCLK
00
F
10
8x40 bit
Ring
T
Buffer
01
TXENC8B10BUSE,
TX_BUFFER_USE
TXENC64B66BUSE
Figure 2-11
011 000 1XX
PMA TXCLK0
PCS Dividers &
Clock Control
Phase Align
0001
0010
0000
10GBASE-R
(1)
Gearbox
64B/66B
1100
(1)
Scrambler
TXSCRAM64B66BUSE,
TXGEARBOX64B66BUSE,
TXDATA_SEL
ug076_ch8_02_071807
and Figure 2-12.
TXP
PISO
TXN
PMA
75