Figure 2-11: Receive Clocking Decision Flow (Page 1 Of 2) - Xilinx Virtex-4 RocketIO User Manual

Chapter 2: Clocking, Timing, and Resets
START
is line
rate > 5 G
YES
ENABLE _ DCDR
= FALSE
RXDIGRX = FALSE
RXOUTDIV 2 SEL
= / 1
VCO rate = line
rate / 2
Set RXPLLNDIVSEL
= VCO rate/refclk
YES
Turn off
RXMCLK
( 2 )
YES
RXCLKMODE [ 0 ]
= 1
RXCLKMODE [ 3 ]
= 0
(cont'd on next page)
78
NO
is line rate
NO
>2.5G
YES
Is line rate
>1.25G
YES
ENABLE_DCDR
= FALSE
RXDIGRX=FALSE
ENABLE_DCDR
= FALSE
RXDIGRX=FALSE
RXOUTDIV 2 SEL
RXOUTDIV 2 SEL
= / 4
= / 2
VCO rate = 2 * line
VCO rate = line
rate
rate
NO
(1)
NO
?
RXCLKMODE [ 0 ]
= 0
RXCLKMODE [ 3 ]
= 0

Figure 2-11: Receive Clocking Decision Flow (Page 1 of 2)

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NO
ENABLE_DCDR
= TRUE
RXDIGRX
= TRUE
NO
Is line rate
>0.625G
YES
line rate
<0.625G
SAMPLE _ 8 X
= TRUE
SAMPLE _ 8 X
= TRUE
RXOUTDIV 2 SEL
RXOUTDIV 2 SEL
= / 1 = / 2
VCO rate = 4 * line VCO rate =
rate 8 * line rate
Is fabric NO
interface
4 bytes?
2 byte fabric
YES
interface
DIGRX _ FWDCLK
YES
= 00
DIGRX _ FWDCLK
= 01
1. Modify refclk frequency for valid (8, 10, 16, 20, 32, 40)
RXPLLNDIVSEL values. The lower value generates better
performance.
2. RXMCLK clock port is not supported.
3. Channel Bonding, Clock Correction, and 8-byte fabric
interface are not available in low latency mode.
4. RXRECCLK1 and RXRECCLK2 are never the same in the
mode when RXRECCLK2_USE_SYNC is set to false
regardless of low latency mode usage. There is no use model
that needs these to be the same.
5. Max serial rate for 1 byte I/F is 2.5 Gb/s.
Max serial rate for 2 byte I/F is 5.0 Gb/s.
6. This mode requires that USRCLK be provided by the fabric.
7. Channel Bonding requires that the USRCLK is provided via the
fabric.
8. 64B/66B encoding/decoding is not supported.
Virtex-4 RocketIO MGT User Guide
NO
1 byte fabric
interface
DIGRX _ FWDCLK
= 10
ug076_ch2_08a_071807
UG076 (v4.1) November 2, 2008
R