Mgt Clock Ports And Attributes - Xilinx Virtex-4 RocketIO User Manual

Chapter 2: Clocking, Timing, and Resets
Table 2-1: MGTCLK Ports and Attributes (Continued)
GT11CLK
SYNCLK1OUTEN
SYNCLK2OUTEN

MGT Clock Ports and Attributes

The RocketIO MGT has four groups of clocks: reference, user, MGT output, and CRC logic
clocks. The clock ports are shown in
clock for the three PLLs in a tile.
Table 2-2: MGT Clock Ports
Clock
Reference Clocks
GREFCLK
REFCLK1
REFCLK2
User Clocks
RXUSRCLK
RXUSRCLK2
TXUSRCLK
TXUSRCLK2
MGT Output Clocks
RXRECCLK1
RXPCSHCLKOUT
RXRECCLK2
TXOUTCLK1
TXPCSHCLKOUT
TXOUTCLK2
RXMCLK
CRC Clocks
RXCRCCLK
RXCRCINTCLK
TXCRCCLK
TXCRCINTCLK
64
GT11CLK_MGT I/O
SYNCLK1OUTEN
N/A
SYNCLK2OUTEN
N/A
I/O
I Alternate reference clock. (Used only for 1 Gb/s or slower applications.)
Reference clock for the TX and RX PLLs. The multiplication ratio for parallel-to-
I
serial conversion is application dependent.
Reference clock for the TX and RX PLLs. The multiplication ratio for parallel-to-
I
serial conversion is application dependent.
I Clocks the receiver PCS internal logic.
I Clocks the receiver PCS/ FPGA fabric interface.
I Clocks the transmitter PCS internal logic.
I Clocks the transmitter PCS/FPGA fabric interface.
Fabric port that can be routed to the regional and global clock buffers using fabric
O
resources. Recovered clock from incoming data.
O Reserved. This clock port is not supported.
Recovered clock from incoming data. Same as PCS RXCLK except in DCDR mode.
O
Please see section
Fabric port that can be routed to the regional and global clock buffers using fabric
O resources. Transmitter output clock derived from PLL based on transmitter
reference clock. Can be used to clock the FPGA.
O Reserved. This clock port is not supported.
Transmit output clock from the PCS TXCLK domain in the PCS. Source is
O
dependant on the PCS clock configuration.
O Reserved. This clock port is not supported.
I Clocks the internal receiver CRC logic.
I Clocks the CRC/FPGA fabric interface.
I Clocks the internal transmitter CRC logic.
I Clocks the CRC/FPGA fabric interface.
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Description
Allows the SYNCLK1OUT to drive the REFCLK1 column bus.
Allows the SYNCLK2OUT to drive the REFCLK2 column bus.
Table 2-2. Table 2-3
Description
"Digital Receiver" in Chapter
show how to select the reference
3.
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
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