Figure 12-3: Via Structures For Bga Adjacent Sio; Smt Xenpak70 Connector Design Example - Xilinx Virtex-4 RocketIO User Manual

Chapter 12: Guidelines and Examples
coupling and the adjacent PCB vias offer 2-4 times more coupling. Simulation suggests that
the amount of coupling due to adjacent PCB vias is affected by which layer the SIO escape
is located, and on how the analog supplies are delivered to the MGTs. Simulation predicts
that coupling can be reduced by using the upper PCB routing layers to route SIO and/or
by using a higher layer to distribute MGT analog power supplies. When a design dictates
that SIO with a BGA adjacency to MGT analog supply pins are to be used for high
drive/high speed applications, the following guidelines apply:
•
•
•
Figure
mechanism is mutual inductive coupling and this occurs in the area between the active
signal path and the power via. The secondary coupling mechanism is capacitive and is also
shown in
recommendations are designed to minimize this effect.

SMT XENPAK70 Connector Design Example

Figure 12-4
and the connector mounting hole, differential vias other than the preferred GSSG-type
differential via are used.
262
Apply power to the MGT analog supplies with a plane or wide buses a few layers
below the top of the board. Using a blind via to the MGT analog supplies is better
than using a through via.
If a through via to supply the MGT analog supply pins must be used, use an upper
layer to supply analog power to these vias. Route SelectIO nets in the uppermost layer
available after MGT signal and MGT analog supply routing is implemented.
If supplying MGT power from the bottom of the board, route these SelectIO nets in
the highest available routing layer.
12-3, depicts the coupling regions for BGA adjacent SIO. The primary coupling
Figure 12-3. The primary coupling mechanism is much larger, and the
SelectIO signal
SelectIO
signal path
Mutual inductive coupling in
this area between active signal
path and power via (primary)

Figure 12-3: Via Structures for BGA Adjacent SIO

shows a XENPAK70 connector entry. Due to space constraints on this board
www.xilinx.com
RocketIO power pin
Capacitive coupling in this area
to power "via stub" (secondary)
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
R
RocketIO
power plane
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