Determining Correct Clk_Cor_Min_Lat And Clk_Cor_Max_Lat - Xilinx Virtex-4 RocketIO User Manual

Chapter 3: PCS Digital Design Considerations
In some cases, more than two clock correction sequences can be defined in a protocol. For
this case, the CLK_COR_SEQ_MASK attributes can "mask" portions of the sequence. For
example, there are three clock correction sequences:
•
•
•
Any of these sequences should be treated as a clock correction sequence. However, the
CLK_COR_SEQ_*_* only allow two sequences. Because three of the four bytes are always
the same, CLK_COR_SEQ_1_MASK[3] can be set to a logic 1, corresponding to the last
byte.
Table 3-17: Clock Correction Mask Example Settings (Mask Enabled)
Notes:
1. Ensure that sequences that are not clock correction do not fall into this mask definition.

Determining Correct CLK_COR_MIN_LAT and CLK_COR_MAX_LAT

To determine the correct CLK_COR_MIN_LAT value, several requirements must be met.
•
•
•
•
The defaults of 36 and 44 meet these requirements for a CHAN_BOND_LIMIT of 7.
126
K28.5, D.21.4, D21.5, D25.1;
K28.5, D.21.4, D21.5, D25.2;
K28.5, D.21.4, D21.5, D25.3.
Table 3-17 shows the setting for this case. Note that bit 3 corresponds to SEQ_*_4.
Attribute
CLK_COR_SEQ_1_1
CLK_COR_SEQ_1_2
CLK_COR_SEQ_1_3
CLK_COR_SEQ_1_4
CLK_COR_SEQ_1_MASK
CLK_COR_SEQ_LEN
CLK_COR_MIN_LAT must be greater than or equal to 20 for 1, 2, or 4-byte mode. It
must be 24 for 8-byte mode.
CLK_COR_MIN_LAT and CLK_COR_MAX_LAT must be multiples of CCS/CBS
lengths and ALIGN_COMMA_WORD. The following conditions must be satisfied:
♦
CLK_COR_MIN_LAT (or) CLK_COR_MAX_LAT = n * CLK_COR_SEQ_LEN
(if clock correction is used)
♦
CLK_COR_MIN_LAT (or) CLK_COR_MAX_LAT = m *
CHAN_BOND_SEQ_LEN (if channel bonding is used)
♦
CLK_COR_MIN_LAT (or) CLK_COR_MAX_LAT = l * ALIGN_COMMA_WORD
(if the internal word alignment feature is used)
where:
n, m, l = integer values starting from 1
( CLK_COR_MAX_LAT – CLK_COR_MIN_LAT ) ≥ 2 * CLK_COR_SEQ_LEN
For symbols of less than 8 bytes, (CLK_COR_MIN_LAT – CHAN_BOND_LIMIT) > 20
if CHAN_BOND_MODE is not OFF. For symbols of 8 bytes, (CLK_COR_MIN_LAT –
CHAN_BOND_LIMIT) > 24.
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Setting
Defines a K28.5.
00110111100
Defines a D21.4.
00010010101
Defines a D21.5.
00010110101
Defines a D21.5.
00010110101
Check compare first 3 bytes. If a 4-byte
sequence contains the first 3 bytes, it is
determined to be a clock correction
1000
sequence. The fourth byte can be any
character.
Complete sequence is 4 bytes.
4
Virtex-4 RocketIO MGT User Guide
Definition
UG076 (v4.1) November 2, 2008
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