Simulation Models; Smartmodels; Hspice; Implementation Tools - Xilinx RocketIO User Manual

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Simulation and Implementation

Simulation Models

SmartModels

SmartModels are encrypted versions of the actual HDL code. These models allow the user to
simulate the actual functionality of the design without having access to the code itself. A simulator
with SmartModel capability is required to use SmartModels.
The models must be extracted before they can be used. For information on how to extract the
SmartModels under ISE 5.1i, see

HSPICE

HSPICE is an analog design model that allows simulation of the RX and TX high-speed transceiver.
To obtain these HSPICE models, go to the SPICE Suite Access web page at
http://support.xilinx.com/support/software/spice/spice-request.htm.

Implementation Tools

Par
For place and route, the transceiver has one restriction. This is required when channel bonding is
implemented. Because of the delay limitations on the CHBONDO to CHBONDI ports, linking of
the Master to a Slave_1_hop must run either in the X or Y direction, but not both.
In
the other slave (a Slave_2_hops), both X and Y displacement is needed. This slave needs one level
of daisy-chaining, which is the basis of the Slave_2_hops setting.
Figure 4-2
more transceivers (16) per chip.
RocketIO™ Transceiver User Guide
UG024 (v2.3.2) June 24, 2004
Figure 4-1, the two Slave_1_hops are linked to the master in only one direction. To navigate to
shows the channel bonding mode and linking for a 2VP50, which (optionally) contains
www.xilinx.com
1-800-255-7778
Solution Record 15501.
Chapter 4
119