Transmit Latency And Output Skew; Tx Low-Latency Buffered Mode Without Channel Deskew; Overview; Clocking - Xilinx Virtex-4 RocketIO User Manual

Chapter 8: Low-Latency Design

Transmit Latency and Output Skew

The channel-to-channel transmit output skew is an important concern for many channel-
bonding applications. Many traditional SERDES products manage this issue by using a
single PLL for multiple serial lanes. In the Virtex-4 MGT, a single transmit PLL is shared by
both MGTs in a tile.
Many applications, however, require that more than two channels be synchronized. This
means that the Virtex-4 MGTs have to handle two phase-disparate PLLs, generating serial
data with minimum skew. This is addressed by using the phase alignment circuitry
controlled via the TXSYNC fabric input. The TX outputs are aligned to one of two global
timing sources, GREFCLK or the PCS TXCLK. The selection of the appropriate alignment
source depends on the clocking mode requirements for the application.
The following most frequently anticipated use cases can serve as a guide to determine a
custom path, if required.

TX Low-Latency Buffered Mode without Channel Deskew

Overview

The TXSYNC functionality is not required in this mode, resulting in bypassed functionality
without the need for synchronizing the PCS and PMA clocks. An additional penalty in
latency is incurred, and the skew between channels is not specifically addressed.

Clocking

To use the internal PCS dividers for TXUSRCLK:
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To provide External TXUSRCLK, set TX_CLOCK_DIVIDER = 00 and provide the
appropriate frequency clock at the TXUSRCLK port. This could require the use of an
additional DCM or PMCD.
Note:
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If 4-byte mode is required, TX_CLOCK_DIVIDER = 11
If 2-byte mode is required, TX_CLOCK_DIVIDER = 01
If 1-byte mode is required, TX_CLOCK_DIVIDER = 10
If using a DCM, only CLK0 and CLKDV outputs should be used.
www.xilinx.com Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
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