Xilinx Virtex-4 RocketIO User Manual page 17
Multi-gigabit transceiver
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- Configuration user manual (114 pages) ,
- User manual (176 pages)
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Chapter 6: Analog and Board Design Considerations
Figure 6-1: MGT Tile Power and Serial I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Figure 6-2: Internal Receiver AC Coupling with External DC Coupling between
Transmitter and Receiver Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Figure 6-3: Power Supply Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Figure 6-4: Power Filtering Network for One MGT Tile . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 6-5: Layout for Power Filtering Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 6-6: Optimizing Filtering for an MGT Column. . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Figure 6-7: Reference Clock Oscillator Interface (Up to 400 MHz) . . . . . . . . . . . . . . . . . 170
Figure 6-8: Reference Clock VCSO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 6-9: Transmit Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 6-10: Simplified Receive Termination Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Figure 6-11: AC-Coupled Serial Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Figure 6-12: AC Coupling Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Figure 6-13: DC-Coupled Serial Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Figure 6-14: Single-Ended Trace Geometry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Figure 6-15: Obstacle Route Geometry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Chapter 7: Simulation and Implementation
Chapter 8: Low-Latency Design
Figure 8-1: PCS Receive Clocking Domains and Data Paths. . . . . . . . . . . . . . . . . . . . . . . 192
Figure 8-3: Using GREFCLK as Synchronization Clock (Use Models TX_2A-H) . . . . . 200
Figure 8-4: TX Low Latency Buffered Mode: Use Models TX_1A, TX_2A . . . . . . . . . . . 202
Figure 8-5: TX Low Latency Buffered Mode: Use Models TX_1B, TX_2B. . . . . . . . . . . . 203
Figure 8-6: TX Low Latency Buffered Mode: Use Models TX_1C, TX_2C . . . . . . . . . . . 204
Figure 8-7: TX Low Latency Buffered Mode: Use Models TX_1D, TX_2D . . . . . . . . . . . 205
Figure 8-8: TX Low Latency Buffered Mode: Use Model TX_2E. . . . . . . . . . . . . . . . . . . . 206
Figure 8-9: TX Low Latency Buffered Mode: Use Model TX_2F. . . . . . . . . . . . . . . . . . . . 207
Figure 8-10: TX Low Latency Buffered Mode: Use Model TX_2G . . . . . . . . . . . . . . . . . . 208
Figure 8-12: Using PCS TXCLK as Synchronization Clock (Use Models TX_3A-B). . . 210
Figure 8-13: TX Low Latency Buffer Bypass Mode: Use Model TX_3A . . . . . . . . . . . . . 212
Figure 8-14: TX Low Latency Buffer Bypass Mode: Use Model TX_3B . . . . . . . . . . . . . . 213
Figure 8-15: TXSYNC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Figure 8-16: RX Low Latency Buffered Mode: Use Model RX_1A . . . . . . . . . . . . . . . . . . 221
Figure 8-17: RX Low Latency Buffered Mode: Use Model RX_1B . . . . . . . . . . . . . . . . . . 222
Figure 8-19: RX Low Latency Buffer Bypass Mode: Use Model RX_2A . . . . . . . . . . . . . 225
Figure 8-20: RX Low Latency Buffer Bypass Mode: Use Model RX_2B . . . . . . . . . . . . . 226
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
www.xilinx.com
17
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