Fabric Clocks - Xilinx Virtex-4 RocketIO User Manual

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Fabric Clocks

There are two cases, illustrated here in
Clock from Global
Clock Tree Including
Other MGT Column
Clock from Global
Clock Tree Including
Other MGT Column
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
a. Direct connection to single tile (two MGTs) from GREFCLK pin, which does not
use the GT11CLK_MGT module.
b. REFCLK1 or REFCLK2 column bus routing by connecting the fabric clock to the
REFCLK input of the GT11CLK module.
(a)
GT11_inst1
(MGTB of tile)
GREFCLK
GT11_inst2
(MGTA of tile)
GREFCLK
GT11_inst3
(MGTB of tile)
GREFCLK
Note: inst1 cannot share GREFCLK
with inst2 and inst3 without using
fabric clocking resources.
Figure 2-3: REFCLK and GREFCLK Options for an MGT Tile
www.xilinx.com
Figure 2-3:
GT11CLK_inst1
Clock from Global
Clock Tree Including
Other MGT Column
SYNCLK1OUTEN = ENABLE
SYNCLK2OUTEN = DISABLE
REFCLKSEL = REFCLK
GT11CLK_inst2
Clock from Global
Clock Tree Including
Other MGT Column
SYNCLK1OUTEN = DISABLE
SYNCLK2OUTEN = ENABLE
REFCLKSEL = REFCLK
Clock Distribution
(b)
GT11_inst1
REFCLK1
REFCLK2
GT11_inst2
REFCLK1
REFCLK2
GT11_inst3
REFCLK1
REFCLK2
GT11CLK input REFCLK
drives the entire column
via the SYNCLK clock trees.
UG076_CH2_06_050806
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