Crc Reset; Resetting The Transceiver; Transmit Reset Sequence: Tx Buffer Used - Xilinx Virtex-4 RocketIO User Manual

R
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•
•
•
See
clocking domains and datapaths.
For Digital CDR, asserting RXRESET causes the PMA parallel clock RXRECCLK1 to stop
toggling (remain at a constant value).

CRC Reset

CRCRESET resets the CRC section of the transmitter (TXCRCRESET) and receiver
(RXCRCRESET). (See
Proper assertion and deassertion of these resets are necessary to set up the CRC for use.

Resetting the Transceiver

This section describes different use cases of resetting the transceiver.

Transmit Reset Sequence: TX Buffer Used

Figure 2-14
used. Refer to the following points in conjunction with this figure:
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•
See
requirement.
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
RX Buffer — RXUSRCLK and PCS RXCLK domains
Channel Bonding & Clock Correction Logic — RXUSRCLK and PCS RXCLK domains
Comma Detect Align — PCS RXCLK Domain
Digital CDR
Figure 2-7, "PCS Receive Clocking Domains and Datapaths," page 74
Chapter 5, "Cyclic Redundancy Check
provides a flow chart of the transmit reset sequence when the TX buffer is
The flow chart uses TXUSRCLK as reference to the wait time for each state. Do not use
TXUSRCLK as the clock source for this block; this clock might not be present during
some states. Use a free-running clock (for example, the system's clock) and make sure
that the wait time for each state equals the specified number of TXUSRCLK cycles.
It is assumed that the frequency of TXUSRCLK is slower than the frequency of
TXUSRCLK2. If TXUSRCLK2 is slower, use that clock as reference to the wait time for
each state.
tx_usrclk_stable is a status signal from the user's application that is asserted High
when both TXUSRCLK and TXUSRCLK2 clocks are stable. For example, if a DCM is
used to generate both the TXUSRCLK and TXUSRCLK2 clocks, then the DCM
LOCKED signal can be used here.
tx_pcs_reset_cnt is a counter from the user's application that is incremented every
time both TXBUFERR and TXLOCK signals are asserted. It is reset when the block
cycles back to the TX_PMA_RESET state.
In synchronous systems like the GPON application where
RXRECCLK1/RXRECCLK2 is used for the TX PLL, the TX_SYSTEM_RESET state
should stall until there is a stable RXLOCK signal from the RX PLL (RXLOCK == 1 for
16K [16 x 1024] REFCLK cycles). The condition in going from TX_SYSTEM_RESET to
TX_PMA_RESET needs to be modified to:
♦
Analog CDR Mode:
!system_reset && (RXLOCK == 1 for 16K [16 x 1024] REFCLK cycles)
♦
Digital CDR Mode:
!system_reset && RXLOCK == 1
"RX Reset Sequence Background," page 100
www.xilinx.com
(CRC).")
for information on the 16K REFCLK cycles
Resets
for PCS receive
85