Simulating In Verilog; Simulating In Vhdl - Xilinx Virtex-4 RocketIO User Manual

Chapter 7: Simulation and Implementation

Simulating in Verilog

The global set/reset (GSR) and global 3-state (GTS) signals are defined in the
$XILINX/verilog/src/glbl.v module. The glbl.v module connects the global
signals to the design, which is why it is necessary to compile this module with the other
design files and load it along with the design.v and testfixture.v files for
simulation.
Defining GSR/GTS in a Test Bench
There are two ways to do this:
1.
2.

Simulating in VHDL

The ROCBUF cell is used to control the emulated GSR signal in a test bench. This
component creates a buffer for the global set/reset signal, and provides an input port on
the buffer to drive the global set reset line. This port must be declared in the entity list and
driven through the test bench.
VHDL Module: EX_ROCBUF.vhd
182
In most cases, GSR and GTS need not be defined in the test bench. The glbl.v file
declares the global GSR and GTS signals and automatically pulses GSR for 100 ns. This
is sufficient for back-end simulations, and is generally sufficient for functional
simulations as well.
If GSR or GTS needs to be emulated in the test bench, the following snippet of code
must be added to the testfixture.v file:
assign glbl.GSR = gsr_r;
assign glbl.GTS = gts_r;
initial
begin
gts_r = 1'b0;
gsr_r = 1'b1;
#(16*CLOCKPERIOD);
gsr_r = 1'b0;
end
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
library UNISIM;
use UNISIM.all;
entity EX_ROCBUF is
port (
CLOCK, ENABLE, SRP,RESET : in std_logic;
C_OUT: out std_logic_vector (3 downto 0)
);
end EX_ROCBUF;
architecture A of EX_ROCBUF is
signal GSR : std_logic;
signal COUNT : std_logic_vector (3 downto 0);
component ROCBUF
port (
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