Xilinx Virtex-4 RocketIO User Manual page 24

Section II:
Board Level Design
Chapter 9: Methodology Overview
Chapter 10: PCB Materials and Traces
Chapter 11: Design of Transitions
Chapter 12: Guidelines and Examples
Table 12-1: Model-Derived Loss for Differential Vias of Various Dimensions . . . . . . 259
Section III:
Appendixes
Appendix A: RocketIO Transceiver Timing Model
Table A-1: MGT Clock Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Table A-2: RocketIO DCLK Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Table A-3: RocketIO RXCRCCLK Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . 276
Table A-4: RocketIO TXCRCCLK Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . 277
Table A-5: RocketIO RXUSRCLK Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . 277
Table A-6: RocketIO RXUSRCLK2 Switching Characteristics . . . . . . . . . . . . . . . . . . . . . 278
Table A-7: RocketIO TXUSRCLK Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . 280
Appendix B: 8B/10B Valid Characters
Table B-1: Valid Data Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Table B-2: Valid Control "K" Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Appendix C: Dynamic Reconfiguration Port
Table C-1: Dynamic Reconfiguration Port Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Table C-2: Dynamic Reconfiguration Port Memory Map: MGTA Address 40–44. . . . . 294
Table C-3: Dynamic Reconfiguration Port Memory Map: MGTA Address 45–49. . . . . 295
Table C-4: Dynamic Reconfiguration Port Memory Map: MGTA Address 4A–4E . . . . 296
Table C-5: Dynamic Reconfiguration Port Memory Map: MGTA Address 4F–53 . . . . 297
Table C-6: Dynamic Reconfiguration Port Memory Map: MGTA Address 54–58. . . . . 298
Table C-7: Dynamic Reconfiguration Port Memory Map: MGTA Address 59–5D . . . . 299
Table C-8: Dynamic Reconfiguration Port Memory Map: MGTA Address 5E–62 . . . . 300
Table C-9: Dynamic Reconfiguration Port Memory Map: MGTA Address 63–67. . . . . 301
Table C-10: Dynamic Reconfiguration Port Memory Map: MGTA Address 68–6C . . . 302
Table C-11: Dynamic Reconfiguration Port Memory Map: MGTA Address 6D–71 . . . 303
24 www.xilinx.com Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
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