Figure 8-5: Tx Low Latency Buffered Mode: Use Models Tx_1B, Tx_2B - Xilinx Virtex-4 RocketIO User Manual

Multi-gigabit transceiver

Hide thumbs Also See for Virtex-4 RocketIO:

Table of Contents

TXDATA (2,4,8B)

Virtex-4 RocketIO MGT User Guide

UG076 (v4.1) November 2, 2008

shows the buffered-mode flow through the TX using the 8B/10B Encoder.

TX_CLOCK_DIVIDER

Note: (1) 64B/66B encoding/decoding is not supported.

Figure 8-5: TX Low Latency Buffered Mode: Use Models TX_1B, TX_2B

www.xilinx.com

TXCLK0_FORCE_PMACLK,

TX_CLOCK_DIVIDER

TXENC8B10BUSE,

TX_BUFFER_USE

TXENC64B66BUSE

Transmit Latency and Output Skew

PCS Dividers &

Clock Control

TXSCRAM64B66BUSE,

TXGEARBOX64B66BUSE,

ug076_ch8_05_071807

Table of Contents