Functionality - Xilinx Virtex-4 RocketIO User Manual

R
Table 5-2: CRC Attributes (Continued)
Notes:
1. RapidIO uses a 16-bit CRC, which cannot be generated or checked using the MGT's CRC-32 block.

Functionality

The 32-bit CRC block is a CRC generator using the following polynomial:
An important feature of the block is its ability to work at twice the speed of
RX/TXCRCINTCLK when the fabric data width is twice the internal data width, as shown
in
TRUE, the ratio between RXCRCINTCLK / TXCRCINTCLK and RXCRCCLK /
TXCRCCLK frequencies is 1:2. The maximum interface data width is 64 bits. This allows a
maximum supported data rate of 16 Gb/s at 64-bit RXCRCIN / TXCRCIN data width,
with RXCRCINTCLK / TXCRCINTCLK and RXCRCCLK / TXCRCCLK at 250 MHz and
500 MHz respectively. See
data widths. Data widths supported, shown in
bits. The data width can be changed by CRCDATAWIDTH at any time to support change
in data rate and end-of-packet residue. (Packet length is assumed to be a multiple of bytes.)
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
Attribute
Sets the transmitter CRC initial value. This must be defined for each
protocol that uses 32-bit CRC:
Ethernet
TXCRCINITVAL
PCI-Express
Infiniband
Fibre Channel
Serial ATA
RapidIO
TXCRCCLKDOUBLE Allows ratio of 2:1 for TXCRCCLK and TXCRCINTCLK.
TRUE/FALSE. Select single clock mode for TX CRC.
TXCRCSAMECLOCK
See
Enables the TX CRC block. Default = FALSE. User must assert
TXCRCENABLE
TRUE in the design to enable CRC.
FALSE/TRUE. Inverts the transmitter CRC clock.
TXCRCINVERTGEN
32 26 23
G(x) = x + x + x + x
Figure 5-2. When the attribute RXCRCCLKDOUBLE / TXCRCCLKDOUBLE is set to
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Function
Protocol
32'h 0000 0000
(1)
TRUE: the fabric interface clock rate is the same as the internal
clock rate (TXCRCCLOCKDOUBLE is FALSE); the CRC fabric
interface and internal logic are being clocked using
TXCRCINTCLK. This attribute is typically set to TRUE when
TXCRCCLOCKDOUBLE is set to FALSE.
FALSE: the clocks are being supplied to both the TXCRCCLK
and TXCRCINTCLK ports.
Chapter 5, "Cyclic Redundancy Check (CRC),"
FALSE = CRC clock not inverted (default)
TRUE = CRC clock inverted. During normal operation this
should always be set to FALSE.
22 16 12 11 10
+ x + x + x + x
Table 5-3 for all possible combinations of clock frequency and
Table
Functionality
Default Init Value
32'h FFFF FFFF
32'h 5232 5032
N/A
for details.
8 7 5 4 2
+ x + x + x + x + x + x + 1.
5-4, are 8, 16, 24, 32, 40, 48, 56, and 64
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