Chapter 12: Guidelines And Examples; Summary Of Guidelines - Xilinx Virtex-4 RocketIO User Manual

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Guidelines and Examples
This section discusses high-level PCB guidelines and strategies. Design examples are
provided that show how these guidelines are applied and how transitions can be modified
to accommodate specific applications.

Summary of Guidelines

This high-level summary provides a quick reference to some of the guidelines already
covered in previous sections, and also introduces some general strategies when designing
high-speed serial channels.
When defining the stack-up, high-speed stripline layers are kept near the bottom of the
board. If all high-speed traces can be routed on the top and/or the bottom microstrip
layers, there is no need for a stripline layer. Wider traces are preferred and widths of 6 mils
to 12 mils are typical, although widths down to 4 mils are often used for lower data rates.
Unless there are tight space constraints, the differential trace pairs need not be closely
coupled. For example, instead of using a 5 mil trace width with 5 mil spacing, the same
characteristic trace impedance can be obtained using a 7 mil width with 12 mil spacing.
High-speed differential pairs and transitions must be spread apart on adjacent channels
generously to limit crosstalk, even if the paths become a little longer. In most cases, signal
pairs eventually have to be spread out to match connector pin spacings.
Signal loss increases exponentially with increasing capacitance, so compute excess
capacitance along the channel. Identify the largest sources of excess capacitance; removing
100 fF from a large capacitance source provides much more improvement than removing
100 fF from a transition with a low amount of capacitance.
Another way to counteract the exponential increase of loss with increasing capacitance is
to split grouped transitions. As an example, 1000 fF at 5 GHz has a loss of 2.08 dB, but four
250 fF capacitors spread far enough apart create just 0.164 dB loss each, for a total loss of
0.66 dB.
Simulate the channel to confirm expected losses due to line and transition attenuation.
Also observe any ripple or notches in the frequency sweep, which is indicative of multiple
reflections in the time domain. Reduce the ripple as much as possible by reducing the
incidence of multiple capacitances separated by short lengths of transmission line.
For transitions, large clearances of planes must be provided around and below transitions
to limit excess capacitance. As just mentioned, it is generally desirable to space transitions
apart within the same channel. For example, differential vias must not be placed next to
DC blocking capacitors or connectors. However, in some specific cases, performance was
acceptable with this placement.
To further limit excess capacitance in vias, the unused pads on vias should be removed and
the via stub length is kept to a minimum. By routing from the top microstrip to the bottom
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
www.xilinx.com
Chapter 12
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