Xilinx 7 Series User Manual
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Xilinx 7 Series User Manual

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GTP Transceivers
User Guide
UG482 (v1.9) December 19, 2016

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  • Page 1 7 Series FPGAs GTP Transceivers User Guide UG482 (v1.9) December 19, 2016...

  • Page 2: Revision History

    Xilinx’s limited warranty, please refer to Xilinx’s Terms of Sale which can be viewed at http://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance;...
  • Page 3 4-5. Changed RXCDR_CFG attribute type from 72- to 83-bit hex in Table 4-12. 08/28/2013 Added devices XC7A35T-CSG325 (Preliminary), XC7A35T-FGG484 (Preliminary), XC7A50T-CSG325 (Preliminary), XC7A50T-FGG484 (Preliminary), XC7A75T-FGG484, and XC7A75T-FGG676. UG482 (v1.9) December 19, 2016 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide...
  • Page 4 DMONITORCLK and DMONFIFORESET to Table 2-31. 12/19/2016 Added Spartan®-7 device family: Updated Preface, Table 5-2, Table 5-3, Table B-1, Table B-2, Figure 5-3, Figure A-1, and Figure A-2. 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com UG482 (v1.9) December 19, 2016...

  • Page 5: Table Of Contents

    ........... 123 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com...
  • Page 6 ........248 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback...
  • Page 7 Appendix B: Placement Information by Device Appendix C: 8B/10B Valid Characters Appendix D: DRP Address Map of the GTP Transceiver 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 8 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...

  • Page 9: Preface: About This Guide

    The Spartan®-7 family is the lowest density with the lowest cost entry point into the 7 series portfolio. The Artix®-7 family is optimized for highest performance-per-watt and bandwidth-per-watt for cost-sensitive, high-volume applications.

  • Page 10: Additional Resources

    Preface: About This Guide Additional Resources To find additional documentation, see the Xilinx website at: http://www.xilinx.com/support/documentation/index.htm. To search the Answer Database of silicon, software, and IP questions and answers, or to create a technical support WebCase, see the Xilinx website at: http://www.xilinx.com/support.

  • Page 11: Overview And Features

    Transceiver and Tool Overview Overview and Features The 7 series FPGAs GTP transceiver is a power-efficient transceiver, supporting line rates between 500 Mb/s and 6.6 Gb/s. The GTP transceiver is highly configurable and tightly integrated with the programmable logic resources of the FPGA.
  • Page 12 GTP transceivers to support configurations for different protocols. The wizard can also be used to create custom configurations. For a complete list of protocols and electrical specifications enabled through predefined settings, please refer to PG168, 7 Series FPGAs Transceivers Wizard LogiCORE IP Product Guide.
  • Page 13 , 7 Series FPGAs Configuration User Guide provides more information on the configuration. UG471, 7 Series FPGAs SelectIO Resources User Guide provides more information on the I/O blocks. UG472, 7 Series FPGAs Clocking Resources User Guide provides more information on the mixed mode clock manager (MMCM).
  • Page 14 The GTPE2_COMMON primitive contains two ring oscillator PLLs (PLL0 and PLL1). GTPE2_COMMON must always be instantiated. Each GTPE2_CHANNEL primitive consists of a transmitter and a receiver. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 15 Figure 1-3: GTPE2_CHANNEL Primitive Topology Refer to Figure 2-9, page 35 for the description of the channel clocking architecture, which provides clocks to the RX and TX clock dividers. 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...

  • Page 16: Series Fpgas Transceivers Wizard

    Transceiver and Tool Overview 7 Series FPGAs Transceivers Wizard The 7 Series FPGAs Transceivers Wizard (hereinafter called the Wizard) is the preferred tool to generate a wrapper to instantiate GTP transceiver primitives called GTPE2_COMMON and GTPE2_CHANNEL. The Wizard is located in the CORE Generator tool. The user is recommended to download the most up-to-date IP update before using the Wizard.
  • Page 17 The correct simulator resolution (Verilog). • The user guide of the simulator and UG626, Synthesis and Simulation Design Guide provide a detailed list of settings for SecureIP support. 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 18 SIM_VERSION String This attribute selects the simulation version to match different steppings of silicon. The default for this attribute is 1.0. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 19 X. This attribute selects the simulation version SIM_VERSION String to match different steppings of silicon. The default for this attribute is 1.0. 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...

  • Page 20: Implementation

    Transceiver and Tool Overview Implementation Functional Description This section provides the information needed to map 7 series GTP transceivers instantiated in a design to device resources, including: • The location of the GTP transceiver Quads on the available device and package combinations.
  • Page 21 PLL0 PLL1 GTPE2_CHANNEL GTPE2_CHANNEL GTPE2_CHANNEL UG482_c1_05_110811 Figure 1-5: Four Channel Configuration Serial Transceiver Channels by Device/Package See UG475, 7 Series FPGAs Packaging and Pinout Specification. 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 22 Chapter 1: Transceiver and Tool Overview www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...

  • Page 23: Chapter 2: Shared Features

    TO GTREFCLK0/1 of GTPE2_COMMON CLKRCV_TRST MGTAVCC 2'b00 Nominal 50 2'b01 TO HROW REFCLK_CTRL[1:0] ODIV2 1'b0 2'b10 Reserved 2'b11 UG482_c2_01_112811 Figure 2-1: Reference Clock Input Structure 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 24 Hrow routing. The selection is controlled automatically by the software depending on whether port O or ODIV2 is connected. Refer to UG472, 7 Series FPGAs Clocking Resources User Guide for more details. Notes: 1. The O and ODIV2 outputs are not phase matched to each other.

  • Page 25: Reference Clock Selection And Distribution

    Reference Clock Selection and Distribution Functional Description The GTP transceivers in 7 series FPGAs provide different reference clock input options. Clock selection and availability differs slightly from 7 series GTX/GTH transceivers in that reference clock routing is east and west bound rather than north and south bound.
  • Page 26 A single reference clock is most commonly used. In this case, the PLL[0/1]REFCLKSEL port can be tied to 3'b001, and the Xilinx software tools handle the complexity of the multiplexers and associated routing. See External Reference Clock Use Model, page 31 for more information.
  • Page 27 GTREFCLK1 Clock External clock driven by IBUFDS_GTE2 for PLL0 and/or PLL1. GTWESTREFCLK0 Clock West-bound clock from the Quad on the right side of the device. 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 28 The user must connect this port to the PLL0REFCLK port on the GTPE2_CHANNEL primitive. PLL1OUTREFCLK Clock The user must connect this port to the PLL1REFCLK port on the GTPE2_CHANNEL primitive. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 29 000: Reserved 001: GTREFCLK0 selected 010: GTREFCLK1 selected 011: GTEASTREFCLK0 selected 100: GTEASTREFCLK1 selected 101: GTWESTREFCLK0 selected 110: GTWESTREFCLK1 selected 111: GTGREFCLK1 selected 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 30 PLL1REFCLKSEL is used instead to dynamically select the reference clock source. Table 2-6 defines the clocking ports for the GTPE2_CHANNEL primitive. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 31 Depending on the line rate requirement, the user design has the flexibility to use different combinations of PLL0 or PLL1 to drive the TX and/or RX datapath, as shown in Figure 2-4. 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 32 GTP Quad GTPE2_ GTPE2_ GTPE2_ GTPE2_ CHANNEL CHANNEL CHANNEL CHANNEL GTPE2_COMMON GTREFCLK0 IBUFDS_GTE2 UG482_c2_05_110811 Figure 2-5: Single GTP Quad with a Single Local Reference Clock www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 33 GTP Quad GTPE2_ GTPE2_ GTPE2_ GTPE2_ CHANNEL CHANNEL CHANNEL CHANNEL GTPE2_COMMON GTREFCLK0 GTREFCLK1 IBUFDS_GTE2 IBUFDS_GTE2 UG482_c2_07_110811 Figure 2-7: Single GTP Quad using Multiple Local Reference Clocks 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...

  • Page 34: Pll

    PLL0 or PLL1 to allow the TX and RX datapaths to operate at asynchronous frequencies using different reference clock inputs. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 35 / N2 UG482_c2_10_011612 Figure 2-10: PLL Block Diagram The PLL has a nominal operating range between 1.6 GHz to 3.3 GHz. The 7 Series FPGAs Transceivers Wizard chooses the appropriate PLL settings based on application requirements. Equation 2-1 shows how to determine the PLL output frequency (GHz).
  • Page 36 Reserved. This port must be set to 5'b111111. This value should not be modified. RCALENB Async Reserved. This port must be set to 1'b1. This value should not be modified. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 37 PLL1_FBDIV_45 Figure 2-10, page 35. Valid settings are 4 and 5. PLL0_LOCK_CFG 9-bit Hex Reserved. The recommended value from the 7 Series FPGAs Transceivers Wizard should be used. PLL1_LOCK_CFG PLL0_REFCLK_DIV Integer PLL reference clock divider M settings as shown in Figure 2-10, page 35.

  • Page 38: Reset And Initialization

    Table 2-9: PLL Attributes (Cont’d) Attribute Type Description PLL0_INIT_CFG 24-bit Hex Reserved. The recommended value from the 7 Series FPGAs Transceivers Wizard should be used. PLL1_INIT_CFG PLL0_DMON_CFG 1-bit Binary Reserved. The recommended value from the 7 Series FPGAs Transceivers Wizard should be used.
  • Page 39 GTP transceiver is in normal operation. TX component reset ports include TXPMARESET and TXPCSRESET. RX component reset ports include RXPMARESET, RXLPMRESET, EYESCANRESET, RXPCSRESET, RXBUFRESET, and RXOOBRESET. 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 40 Port Clock Domain Description GTRESETSEL Async Reset mode enable port. Low: Sequential mode (recommended). High: Single mode. RESETOVRD Async Reserved. Must be tied to ground. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 41 (PLL[0/1]_INIT_CFG[9:0]) Binary PLL reset. Must be a non-zero value. The recommended value from the 7 Series FPGAs Transceivers Wizard should be used. TX Initialization and Reset The GTP transceiver’s TX uses a reset state machine to control the reset process. The GTP transceiver’s TX is partitioned into two reset regions, TX PMA and TX PCS.
  • Page 42 High and then deasserted to start the TX PMA reset process. In sequential mode, activating this port resets both the TX PMA and the TX PCS. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 43 TXPMARESET_TIME 5-bit Binary Reserved. Represents the time duration to apply a TX PMA reset. The recommended value from the 7 Series FPGAs Transceivers Wizard should be used. Must be a non-zero value when GTTXRESET or TXPMARESET is used to initiate the reset process.
  • Page 44 TXRESETDONE is detected High. The associated PLL must indicate locked. The guideline for this asynchronous GTTXRESET pulse width is one period of the reference clock. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 45 Figure 2-17). X-Ref Target - Figure 2-17 TXPCSRESET TXUSERRDY TXRESETDONE TX RESET FSM IDLE WAIT TXPCSRESET IDLE TXPCSRESET_TIME UG482_c2_116_020713 Figure 2-17: TXPCSRESET in Sequential Mode 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 46 After entering or exiting near-end PMA Entire RX GTRXRESET loopback 1. The recommended reset has the smallest impact on the other components of the GTP transceiver. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 47 RX in Sequential Mode To initialize the GTP transceiver’s RX, GTRXRESET must be used in sequential mode. Activating the GTRXRESET input can automatically trigger a full asynchronous RX reset. The 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback...
  • Page 48 All clocks used by the application, including RXUSRCLK and RXUSRCLK2, are shown to be stable or locked when the PLL or the MMCM is used. The user interface is ready to receive data from the GTP transceiver. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 49 This port is driven High and then deasserted to start the full Channel RX reset sequence. RXOSCALRESET Async Reserved. The recommended value from the 7 Series FPGAs Transceivers Wizard should be used. 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 50 RXBUFRESET. Detailed coverage in sequential mode is listed in Table 2-20. In both modes, RXPCSRESET does not start the reset process until RXUSERRDY is High. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 51 Type Description RXOSCALRESET_TIME 5-bit Binary Reserved. The recommended value from the 7 Series FPGAs Transceivers Wizard should be used. Must be a non-zero value when GTRXRESET is used to initiate the reset process. RXOSCALRESET_TIMEOUT 5-bit Binary Reserved. The recommended value from the 7 Series FPGAs Transceivers Wizard should be used.
  • Page 52 5-bit Binary Reserved. Represents the time duration to apply the RX BUFFER reset. The recommended value from the 7 Series FPGAs Transceivers Wizard should be used. Must be a non-zero value when using RXBUFRESET to initiate the reset process. www.xilinx.com...
  • Page 53 When the user wants to trigger RX reset upon configuration, assert and release PLL[0/1]RESET while GTRXRESET is kept asserted. The assertion of GTRXRESET causes RXPMARESETDONE to go Low. 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 54 RXMPARRESET RXCDRFREQRESET RXISCANRESET RXBUFRESET _TIME _TIME _TIME _TIME _TIME RXCDRPHRESET RXLPMRESET RXPCSRESET _TIME _TIME _TIME UG482_c2_120_021113 Figure 2-20: GTP Transceiver Receiver Reset after GTRXRESET Pulse www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 55 RXPMARESET_TIME should be set to 5’h3. This should be the default setting. The sequence above will simulate correctly if SIM_RESET_SPEEDUP is set to FALSE. If SIM_RESET_SPEEDUP is set to TRUE, the above sequence should be bypassed. 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback...
  • Page 56 GTP transceiver’s RX and components affected by them in both sequential mode and single mode. These resets are all asynchronous. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 57 √ √ RX PMA RX CDR Phase Path RX CDR Frequency √ √ Path √ √ √ RX LPM √ √ √ √ RX ISCAN 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 58 Entire RX GTRXRESET RX rate change Entire RX GTRXRESET or reset sequence is performed automatically due to RXRATE RX parallel clock source reset RX PCS RXPCSRESET www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 59 The GTRXRESET should be toggled after the PLL fully completes its reset procedure. After Assertion/Deassertion of RXPD[1:0] After the RXPD signal is deasserted, GTRXRESET must be toggled. 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 60 OOB or electrical idle levels, the RX CDR will be managed automatically when attributes associated with electrical idle are set to appropriate values. Recommended values from the 7 Series FPGA Transceivers Wizard should be used. After Connecting RXN/RXP...

  • Page 61: Power Down

    PCI Express PIPE protocol encoding. 00: P0 (normal operation) 01: P0s (low recovery time power down) 10: P1 (longer recovery time) 11: P2 (lowest power state) 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 62 Counter settings for programmable transition time to/from all states except P2 for PCIe. The recommended value from the 7 Series FPGAs Transceivers Wizard should be used. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 63 [TX/RX]RATE pins for all protocols including the PCIe protocol (Gen2/Gen1 data rates). The recommended value from the 7 Series FPGAs Transceivers Wizard should be used. RX_CLKMUX_PD 1-bit Binary The recommended value from the 7 Series FPGAs Transceivers Wizard should be used.

  • Page 64: Loopback

    Near-end loopback modes loop transmit data back in the transceiver closest to the traffic generator. • Far-end loopback modes loop received data back in the transceiver at the far end of the link. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 65 LOOPBACK[2:0] Async 000: Normal operation 001: Near-End PCS Loopback 010: Near-End PMA Loopback 011: Reserved 100: Far-End PMA Loopback 101: Reserved 110: Far-End PCS Loopback 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 66 Chapter 2: Shared Features Table 2-28: Loopback Attributes Attribute Type Description LOOPBACK_CFG 1-bit Binary Reserved. PMA_LOOPBACK_CFG 1-bit Binary Reserved. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...

  • Page 67: Dynamic Reconfiguration Port

    For write operations, DRPWE and DRPEN should be driven High for one DRPCLK cycle only. See Figure 2-23 for correct operation. Table 2-30 shows the DRP related ports for GTPE2_COMMON. 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 68 1: Write operation when DRPEN is 1. For write operations, DRPWE and DRPEN must be driven High for one DRPCLK cycle only. Please see Figure 2-23 for correct operation. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 69 Figure 2-23: DRP Write Timing Read Operation Figure 2-24 shows the DRP read operation timing. New DRP operation can be initiated when DRPRDY is asserted. 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...

  • Page 70: Digital Monitor

    RX_DEBUG_CFG attribute. The output port DMONITOROUT contains the convergence code(s) for a selected loop. All loops are continuous. A continuous loop has three possible convergence states: min, max, or dithering. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 71 RXLPMHF - LPM high-frequency gain 4'd0 - min 0x0A5 0x00C3 4'd15 - max 4'd0 - min RXLPMLF - LPM low-frequency gain 0x0A5 0x00C4 4'd15 - max 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 72 Verilog code. ////////////////////////////////////////// // Function Prototypes ////////////////////////////////////////// void drpwrite(unsigned int drpaddress, unsigned int drpvalue); usigned int drpread(unsigned int drpaddress); www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 73 7'd0 = –Full scale 7'd63, 7'd64 = 0 7'd127 = +Full scale • RXLPMHF [3:0] = RXLPMLF [3:0] = DMONITOROUT[6:3] 4'd0 = 0 4'd15 = Full scale 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 74 Chapter 2: Shared Features www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...

  • Page 75: Chapter 3: Transmitter

    The key elements within the GTP transceiver TX are: FPGA TX Interface, page 76 TX 8B/10B Encoder, page 83 TX Gearbox, page 86 TX Buffer, page 93 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...

  • Page 76: Fpga Tx Interface

    Interface Width Configuration The 7 series FPGA GTP transceiver contains a 2-byte internal datapath. The FPGA interface width is configurable by setting the TX_DATA_WIDTH attribute. When the 8B/10B encoder is enabled, the TX_DATA_WIDTH attribute must be configured to 20 bits or 40 bits, and in this case, the FPGA TX interface only uses the TXDATA ports.
  • Page 77 Thus TXUSRCLK and TXUSRCLK2 must be multiplied or divided versions of the transmitter reference clock. Ports and Attributes Table 3-4 defines the FPGA TX Interface ports. 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 78 In use models where TX buffer is bypassed, there are additional restrictions on the clocking resources. Refer to TX Pattern Generator, page 103 for more information. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 79 Notes relevant to Figure 3-2: BUFH can be used with certain limitations. For details about placement constraints and restrictions on clocking resources (MMCM, BUFH, BUFG, etc.), refer to UG472, 7 Series FPGAs Clocking Resources User Guide. TXUSRCLK2 TXUSRCLK 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com...
  • Page 80 Figure 3-3: Multiple Lanes—TXOUTCLK Drives TXUSRCLK2 (2-Byte Mode) Notes relevant to Figure 3-3: BUFH can be used with certain limitations. For details about placement constraints and restrictions on clocking resources (MMCM, BUFH, BUFG, etc.), refer to UG472, 7 Series FPGAs Clocking Resources User Guide. TXUSRCLK2 TXUSRCLK www.xilinx.com...
  • Page 81 In the XC7A200T device, BUFH can be used with certain limitations. For details about placement constraints and restrictions on clocking resources (MMCM, BUFH, BUFG, etc.), refer to UG472, 7 Series FPGAs Clocking Resources User Guide. 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com...
  • Page 82 In the XC7A200T device, BUFH can be used with certain limitations. For details about placement constraints and restrictions on clocking resources (MMCM, BUFH, BUFG, etc.), refer to UG472, 7 Series FPGAs Clocking Resources User Guide. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...

  • Page 83: Tx 8B/10B Encoder

    TXCHARISK ports are used to indicate if data on TXDATA are K characters or regular data. The 8B/10B encoder checks received TXDATA byte to match any K character if corresponding TXCHARISK bit is driven High. 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback...

  • Page 84: Running Disparity

    Calculated by the 8B/10B encoder. Inverts running disparity when encoding TXDATA. Forces running disparity negative when encoding TXDATA. Forces running disparity positive when encoding TXDATA. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 85 TXCHARISK[0] corresponds to TXDATA[7:0] A TXCHARISK bit should be driven Low when the corresponding data byte from TXDATA is set to bypass the 8B/10B encoder. 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...

  • Page 86: Tx Gearbox

    [6:0] are used for the 64B/ 67B gearbox. TXSTARTSEQ TXUSRCLK2 This input indicates the first word to be applied after reset for the 64B/66B or 64B/67B gearbox. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 87 On the fifth cycle, the output of the TX gearbox contains two remaining data bits from the first 66-bit block, the header of the second 66-bit block, and 28 data bits from the second 66-bit block. 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback...
  • Page 88 TXHEADER TXDATA UG482_c3_07_110911 Figure 3-7: TX Gearbox Bit Ordering Note relevant to Figure 3-7: Per IEEE802.3ae nomenclature, H1 corresponds to TxB<0>, H0 to TxB<1>, etc. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 89 TX Gearbox (in 7 Series FPGAs GTP Transceiver) Pause Sequence Counter TXSEQUENCE[6:0] (0–32 or 0–66) UG482_c3_08_110911 Figure 3-8: TX Gearbox in External Sequence Counter Mode 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 90 Table 3-11: 64B/67B Encoding Frequency of TXSEQUENCE and Pause Locations Frequency of TX_DATA_WIDTH TXSEQUENCE PAUSE TXSEQUENCE 21, 44, 65 (4-byte) TXUSRCLK2 21, 44, 65 (2-byte) TXUSRCLK2 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 91 After applying 4 bytes of data, the counter increments to 2. Apply data on TXDATA and header information on TXHEADER. On count 21, stop data pipeline. On count 22, drive data on TXDATA. On count 44, stop data pipeline. 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 92 After applying 4 bytes of data, the counter increments to 2. Drive data on TXDATA and header information on TXHEADER. On count 31, stop data pipeline. On count 32, drive data on TXDATA. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...

  • Page 93: Tx Buffer

    103). All TX datapaths must use either the TX buffer or the TX phase alignment circuit. Table 3-12 shows trade-offs between buffering and phase alignment. 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 94 Table 3-14: TX Buffer Attributes Attribute Type Description TXBUF_EN String Use or bypass the TX buffer. TRUE: Uses the TX buffer (default). FALSE: Bypasses the TX buffer (advanced feature). www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...

  • Page 95: Tx Buffer Bypass

    TX Buffer Bypass Functional Description Bypassing the TX buffer is an advanced feature of the 7 series GTP transceiver. The TX phase-alignment circuit is used to adjust the phase difference between the PISO parallel clock domain and the TX XCLK domain to transfer data from the PCS into the PISO. It also performs the TX delay alignment by continuously adjusting the TXUSRCLK to compensate for temperature and voltage variations.
  • Page 96 TX delay alignment up or down. Used as an up or down override when TXPHDLY_CFG[1] = 1 to bypass the TX phase and delay alignment voter. Tied Low when not in use. TXPHALIGNDONE Async TX phase alignment done. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 97 TXUSR: Selects TXUSRCLK as the source of XCLK. Used when bypassing the TX buffer. TXPH_CFG 16-bit Binary Reserved. The recommended value from the 7 Series FPGAs Transceivers Wizard should be used. TXPH_MONITOR_SEL 5-bit Binary Reserved. The recommended value from the 7 Series FPGAs Transceivers Wizard should be used.
  • Page 98 Reserved. Tie to 1'b1. LOOPBACK_CFG 1-bit Binary Reserved. The recommended value from the 7 Series FPGAs Transceivers Wizard should be used. TX Buffer Bypass Use Modes TX phase alignment can be performed on one channel (single lane) or a group of channels sharing a single TXOUTCLK (multi-lane).
  • Page 99 TXUSRCLK and TXUSRCLK2 for all GTP transceivers must come from the same source and must be routed through a low skew clocking resource such as a BUFG for the TX phase alignment circuit to be effective. 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback...
  • Page 100 Master: In a multi-lane application, the buffer bypass master is the lane that is the source of TXOUTCLK. • Slave: All the lanes that share the same TXUSRCLK/TXUSRCLK2, which is generated from the TXOUTCLK of the buffer bypass master. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 101 • Resetting or powering up the PLL • Change of the GTP transceiver reference clock source or frequency • Change of the TX line rate 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 102 13. Assert TXDLYEN for the master lane. This causes TXPHALIGNDONE to be deasserted. 14. Hold TXDLYEN for the master lane High until the rising edge of TXPHALIGNDONE of the master lane is observed. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...

  • Page 103: Tx Pattern Generator

    2-UI square wave test pattern and PCI Express compliance pattern generation (see Table 3-19 Figure 3-16). Clocking patterns are usually used to check PLL random jitter often done with a spectrum analyzer. 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 104 Square Wave with 16 UI or 20 UI period TXDATA UG482_c3_16_110911 Figure 3-17: TX Pattern Generator Block Ports and Attributes Table 3-20 defines the pattern generator ports. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 105 RXPRBSSEL to a non-000 value, and RXPRBS_ERR_LOOPBACK is set to 0 (Figure 3-18). Only the PRBS pattern is recognized by the RX pattern checker. 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...

  • Page 106: Tx Polarity Control

    The TX polarity control can be accessed through the TXPOLARITY input from the fabric user interface. It is driven High to invert the polarity of outgoing data. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...

  • Page 107: Tx Fabric Clock Output Control

    The TX Clock Divider Control block has two main components: serial clock divider control and parallel clock divider and selector control. The clock divider and selector details are illustrated in Figure 3-20. 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 108 GTPE2_CHANNEL primitive. /4 is selected when TX_DATA_WIDTH = 16 or 32. / 5 is selected when TX_DATA_WIDTH = 20 or 40. For details about placement constraints and restrictions on clocking resources (MMCME2, PLLE2, BUFGCTRL, IBUFDS_GTE2, BUFG, etc.), refer to the UG472, 7 Series FPGAs Clocking Resources User Guide. www.xilinx.com...
  • Page 109 TXPLLREFCLK_DIV2 is the input reference clock to PLL0 or PLL1, depending on the TXSYSCLKSEL[1] setting. TXPLLREFCLK is the recommended clock for general usage and is required for the TX buffer bypass mode. 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback...
  • Page 110 TXRATE port. The TRANS_TIME_RATE attribute defines the period of time between a change on the TXRATE port and the assertion of TXRATEDONE. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...

  • Page 111: Tx Phase Interpolator Ppm Controller

    Attribute Type Description TRANS_TIME_RATE 8-bit Hex Reserved. The recommended value from the 7 Series FPGAs Transceivers Wizard should be used. This attribute determines when PHYSTATUS and TXRATEDONE are asserted after a rate change. TXBUF_RESET_ON_RATE_C String When set to TRUE, this attribute enables an...
  • Page 112 128 values output to the TX PI. The most significant bit needs to be pulsed (asserted High and then Low) for the TX PI to register the new 7-bit value of TXPI_PPM_CFG[6:0]. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 113 PI code. This continual phase shifting (fine-tuning) occurs when the lock detect circuit deems the two clocks out of phase and enables the TX phase interpolator PPM controller. 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback...

  • Page 114: Tx Configurable Driver

    TXUSRCLK2 TX de-emphasis control for PCI Express PIPE 2.0 interface. This signal is mapped internally to TXPOSTCURSOR via attributes. 0: 6.0 dB de-emphasis (TX_DEEMPH_0[4:0] attribute) 1: 3.5 dB de-emphasis (TX_DEEMPH_1[4:0] attribute) www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 115 TX_MAINCURSOR_SEL attribute is set to 1'b1. 51 – TXPOSTCURSOR coefficient units – TXPRECURSOR coefficient units < TXMAINCURSOR coefficient units < 80 –TXPOSTCURSOR coefficient units – TXPRECURSOR coefficient units. 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 116 400-700 ULL_2 LOW_2 TX_MARGIN_F TX_MARGIN_ 200-400 100-200 ULL_3 LOW_3 TX_MARGIN_F TX_MARGIN_ 100-200 100-200 ULL_4 LOW_4 default to “DIRECT” mode PMARSVDIN1 Async Reserved. PMARSVDIN0 Async Reserved. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 117 10.46 5'b11100 11.21 5'b11101 12.04 5'b11110 12.96 5'b11111 TXPOSTCURSORINV Async When set to 1'b1, inverts the polarity of the TXPOSTCURSOR coefficient. The default is 1'b0. 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 118 6.02 5'b11100 6.02 5'b11101 6.02 5'b11110 6.02 5'b11111 TXPRECURSORINV Async When set to 1'b1, inverts the polarity of the TXPRECURSOR coefficient. The default is 1'b0. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 119 This attribute has the value of TXBUFDIFFCTRL[2:0] and TXDIFFCTRL[3:0] that has to be mapped when TXMARGIN = 001 and TXSWING = 0. TX_MARGIN_FULL_0 = TXBUFDIFFCTRL[2:0], TXDIFFCTRL[3:0]. The default is 7'b1001111 (1000 mV typical). 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 120 The default is 7'b1000000 (250 mV typical). TX_PREDRIVER_MODE 1-bit Binary This is a restricted attribute. Always set this to 1'b0. Do not modify this attribute. PMA_RSV5 1-bit Binary Reserved. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...

  • Page 121: Tx Receiver Detect Support For Pci Express Designs

    Table 3-30: TX Receiver Detection Ports Port Clock Domain Description TXDETECTRX TXUSRCLK2 Used to tell the GTP transceiver to begin a receiver detection operation. 0: Normal operation. 1: Receiver detection. 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 122 Table 3-31: TX Receiver Detection Attributes Attribute Type Description TX_RXDETECT_CFG 14-bit Binary Reserved. The recommended value from the 7 Series FPGAs Transceivers Wizard should be used. TX_RXDETECT_REF 3-bit Binary Reserved. The recommended value from the 7 Series FPGAs Transceivers Wizard should be used.

  • Page 123: Tx Out-Of-Band Signaling

    Initiates transmission of the COMINIT sequence for SATA/SAS. TXCOMSAS TXUSRCLK2 Initiates transmission of the COMSAS sequence for SAS. TXCOMWAKE TXUSRCLK2 Initiates transmission of the COMWAKE sequence for SATA/SAS. 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 124 1-bit Binary TX OOB configuration. PCS_RSVD_ATTR[8] 1-bit Binary OOB Powerdown 1'b0 - circuit powered down 1'b1 - Circuit powered up (PCIe, SATA/ SAS, protocols/applications using OOB) www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...

  • Page 125: Rx Overview

    RX CDR, page 141 RX Fabric Clock Output Control, page 147 RX Margin Analysis, page 151 RX Polarity Control, page 158 RX Pattern Checker, page 159 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...

  • Page 126: Rx Analog Front End

    ACJTAG RX MGTAVTT ~100 nF 50Ω RX_CM_SEL[1:0] RX_CM_TRIM[3:0] 50Ω MGTAVTT Programmable – – MGTAVTT ~100 nF FLOAT ACJTAG RX UG482_c4_02_110911 Figure 4-2: RX Analog Front End www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 127 4’b1110 – 1000 mV 4’b1111 – 1100 mV TERM_RCAL_CFG[14:0] 15-bit Binary Controls the internal termination calibration circuit. This feature is intended for internal use only. 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 128 X-Ref Target - Figure 4-3 BOARD FPGA ACJTAG RX MGTAVTT ~100 nF RX_CM_SEL [1:0] = 2'b01 50Ω 50Ω MGTAVTT ~100 nF ACJTAG RX UG482_c4_03_020613 Figure 4-3: Use Mode 1 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 129 FPGA ACJTAG RX MGTAVTT ~100 nF 50Ω RX_CM_SEL [1:0] = 2'b11 MGTAVTT – 50Ω MGTAVTT ~100 nF ACJTAG RX UG482_c4_04_110911 Figure 4-4: Use Mode 2 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 130 RX_CM_SEL [1:0] = 2'b11 MGTAVTT – 50Ω RX_CM_TRIM[3:0] MGTAVTT Varies from 4'b0000 – 4'b1111 800mV = 4'b1010 ~100 nF ACJTAG RX UG482_c4_115_020413 Figure 4-5: Use Mode 3 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...

  • Page 131: Rx Out-Of-Band Signaling

    OOB circuit must be powered on. 2'b11: RXELECIDLE outputs a static 1'b0. Use this setting for non-OOB protocols. Table 4-7 defines the OOB signaling attributes. 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 132 To use OOB, the following RX termination conditions need to be applied: • AC-coupled case: Termination voltage should be 800 mV or greater • DC-coupled case: Termination voltage should be 900 mV or greater www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 133 REFCLK. X-Ref Target - Figure 4-7 Clk/2 Output Input UG476_c4_107_071712 Figure 4-7: Toggle Flip-Flop to Divide REFCLK 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 134 OOB operating at line rates > 1.5 Gb/s is an advanced feature. Operation for certain protocols at higher line rates such as PCIe (Gen1 and Gen2) and SATA are addressed in Table 4-8. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 135 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 136 Is Incoming Data RX is in Electrical Idle Valid? RX is in Electrical Idle RX is Not in Electrical Idle UG482_c4_111_020413 Figure 4-10: Flowchart for PCIe Gen1 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 137 PCIe Gen2 Entry Is EIOS Detected? Is RXELECIDLE Detected? RX is in Electrical Idle UG476_c4_113_080712 Figure 4-12: Flowchart for Entry to RX Electrical Idle for PCIe Gen2 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 138 Is Incoming Data RX is Not in Electrical Idle Valid? RX is in Electrical Idle UG482_c4_114_020413 Figure 4-14: Flowchart for SATA 3G or SATA 6G www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...

  • Page 139: Rx Equalizer

    The GTP transceiver receiver has a power-efficient adaptive continuous time linear equalizer (CTLE) to compensate for signal distortion due to high-frequency attenuation in the physical channel. To maintain parity with the 7 series FPGAs GTX and GTH transceivers, the CTLE is referred to as the low-power mode (LPM).
  • Page 140 7 Series FPGAs Transceivers Wizard should be used. RXLPM_LF_CFG 18-bit Binary Reserved. The recommended value from the 7 Series FPGAs Transceivers Wizard should be used. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...

  • Page 141: Rx Cdr

    CDR state machine to have fine phase control. The CDR state machine can track incoming data streams that can have a frequency offset from the local PLL reference clock. 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback...
  • Page 142 Reserved. The recommended value from the 7 Series FPGAs Transceivers Wizard should be used. RXOSINTOVRDEN Async Reserved. The recommended value from the 7 Series FPGAs Transceivers Wizard should be used. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 143 PCI Express reset sequence during electrical idle. RXCDR_FR_RESET_ON_EIDLE Binary Enables automatic reset of the CDR frequency during the optional PCI Express reset sequence during electrical idle. 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 144 (i.e., check a known data pattern). Table 4-13: CDR Recommended Settings for Scrambled/PRBS Data (No SSC RXOUT_DIV REFCLK PPM RXCDR_CFG ±200 ±700 83'h0_0011_07FE_2060_2104_1010 ±1,250 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 145 83'h0_0011_07FE_0860_2110_1010 ±1,250 Notes: 1. For protocol-specific settings, use the recommended value from the 7 Series FPGAs Transceivers Wizard and/or the protocol characterization reports. 2. Spread-spectrum clocking (SSC) is used to reduce the spectral density of electromagnetic interference (EMI). Table 4-14: CDR Recommended Settings for Protocols with SSC...

  • Page 146: Rx Fabric Clock Output Control

    The selection of the /4 or /5 divider block is controlled by the RX_DATA_WIDTH attribute from the GTPE2_CHANNEL primitive. /4 is selected when RX_DATA_WIDTH = 16 or 32. /5 is selected when RX_DATA_WIDTH = 20 or 40. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 147 RX Fabric Clock Output Control For details about placement constraints and restrictions on clocking resources (MMCME2, PLLE2, IBUFDS_GTE2, BUFG, etc.), refer to UG472, 7 Series FPGAs Clocking Resources User Guide. Serial Clock Divider Each transmitter PMA module has a D divider that divides down the clock from the PLL for lower line rate support.
  • Page 148 RXRATE port. The TRANS_TIME_RATE attribute defines the period of time between a change on the RXRATE port and the assertion of RXRATEDONE. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 149 Table 4-18: RX Fabric Clock Output Control Attributes Attribute Type Description TRANS_TIME_RATE 8-bit Hex Reserved. The recommended value from the 7 Series FPGAs Transceivers Wizard should be used. This attribute determines when PHYSTATUS and RXRATEDONE are asserted after a rate change. RXBUF_RESET_ON_RATE_CHANGE String When set to TRUE, this attribute enables automatic RX buffer reset during a rate change event initiated by a change in RXRATE.

  • Page 150: Rx Margin Analysis

    The 7 series FPGAs GTP transceivers RX eye scan provides a mechanism to measure and visualize the receiver eye margin after the equalizer. Additional use modes enable several other methods to determine and diagnose the effects of equalization settings.
  • Page 151 RX Input Equalization Capture FF Rdata Error-detection, Screening Interface De-serialization Sdata Capture FF VERT_OFFSET Rec Clock HORZ_OFFSET UG482_c4_10_112811 Figure 4-21: PMA Architecture to Support Eye Scan 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 152 An error occurs, • A count qualifier occurs, • A fabric port causes a trigger, or • A trigger is forced via an attribute write. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 153 In the READ state, the last two cycles of Rdata can be read from the COE status register, es_rdata[79:0], and the last two cycles of Sdata can be read from the COE status register, es_sdata[79:0]. 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback...
  • Page 154 16-bit register range. Prescale = 2 , so minimum (1+0) (1+31) prescale is 2 = 2 and maximum prescale is 2 = 4,284,967,296. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 155 0: Each bit of the Sdata bus is the recovered data sample. Therefore, if no errors occurred, the Sdata bus would be identical to the Rdata bus. This is used for the scope and waveform views. 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 156 ES_SDATA_MASK, ES_QUALIFIER, ES_QUAL_MASK, es_rdata, and es_sdata: valid Rdata and Sdata width previous data current data [79:64] [39:24] [79:60] [39:20] www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...

  • Page 157: Rx Polarity Control

    Polarity control function uses the RXPOLARITY input, which is driven High from the fabric user interface to invert the polarity. Ports and Attributes Table 4-22 defines the ports required by the RX polarity control function. 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...

  • Page 158: Rx Pattern Checker

    PRBS-7 Pattern Checker (16 bits) PRBS-15 Pattern Checker RXPRBSERR PRBS-23 Pattern Checker PRBS-31 Pattern Checker RXPRBSSEL Polarity SIPO RXDATA Inversion UG482_c4_13_110911 Figure 4-24: RX Pattern Checker Block www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 159 PRBS pattern in the incoming data. If the incoming data is inverted by the transmitter or reversed RXP/RXN, the received data should also 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...

  • Page 160: Rx Byte And Word Alignment

    All Subsequent Data Alignment Block Transmitted First Aligned to Correct Finds Comma Byte Boundary UG482_c4_14_110911 Figure 4-25: Conceptual View of Comma Alignment (Aligning to a 10-Bit Comma) www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...

  • Page 161: Enabling Comma Alignment

    Figure 4-28 shows how the commas are combined when ALIGN_COMMA_DOUBLE is TRUE. X-Ref Target - Figure 4-28 ALIGN_MCOMMA_VALUE ALIGN_PCOMMA_VALUE UG482_c4_17_111011 Figure 4-28: Extended Comma Pattern Definition 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...

  • Page 162: Activating Comma Alignment

    RXBYTEISALIGNED signal, the byte align block might occasionally de-assert the RXBYTEISALIGNED signal even when there is no change in the byte www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...

  • Page 163: Alignment Boundaries

    B yte1 B yte0 (4-b yte) 3 2/4 0 B yte3 B yte2 B yte1 B yte0 (4-b yte) UG482_c4_19_112811 Figure 4-30: Comma Alignment Boundaries 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...

  • Page 164: Manual Alignment

    Note relevant to Figure 4-31: Latency between the slide and the slide result at RXDATA depends on the number of active RX PCS blocks in the datapath. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 165 Note relevant to Figure 4-32: Latency between the slide and the slide result at RXDATA depends on the number of active RX PCS blocks in the datapath. 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 166 Aligns the byte boundary when comma plus is detected. 0: Disabled 1: Enabled. RXMCOMMAALIGNEN RXUSRCLK2 Aligns the byte boundary when comma minus is detected. 0: Disabled 1: Enabled. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 167 This attribute is a 10-bit mask with a default value of 1111111111. Any bit in the mask that is reset to 0 effectively turns the corresponding bit in MCOMMA or PCOMMA to a don't care bit. 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback...
  • Page 168 TRUE: Bring the realignment comma to the FPGA RX. SHOW_REALIGN_COMMA = TRUE should not be used when ALIGN_COMMA_DOUBLE = TRUE or when manual alignment is used. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...

  • Page 169: Rx 8B/10B Decoder

    Defines how long the PCS (in terms of RXUSRCLK clock cycle) waits for the PMA to auto slide before checking the alignment again. Valid settings are from 0 to 15. The default value is 7. The recommended value from the 7 Series FPGAs Transceivers Wizard should be used.

  • Page 170: Rx Running Disparity

    Appendix C, 8B/10B Valid Characters. The non-decoded 10-bit character is piped out of the decoder through the RX data interface with this format: www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...

  • Page 171: Special Characters

    RXCHARISCOMMA High whenever RXDATA is a positive 8B/10B comma. If DEC_MCOMMA_DETECT is TRUE, the decoder drives the corresponding RXCHARISCOMMA bit High whenever RXDATA is a negative 8B/10B comma. 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 172 Active High indicates the corresponding byte shown on RXDATA was not a valid character in the 8B/10B table. RXNOTINTABLE[3] corresponds to RXDATA[31:24] RXNOTINTABLE[2] corresponds to RXDATA[23:16] RXNOTINTABLE[1] corresponds to RXDATA[15:8] RXNOTINTABLE[0] corresponds to RXDATA[7:0] www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...

  • Page 173: Rx Buffer Bypass

    RX Buffer Bypass Functional Description Bypassing the RX elastic buffer is an advanced feature of the 7 series GTP transceiver. The RX phase alignment circuit is used to adjust the phase difference between the PMA parallel clock domain (XCLK) and the RXUSRCLK domain when the RX elastic buffer is bypassed. It also performs the RX delay alignment by adjusting the RXUSRCLK to compensate for the temperature and voltage variations.
  • Page 174 Sets the RX phase alignment. Tied Low when using the auto alignment mode. RXPHALIGNEN Async RX phase alignment enable. Tied Low when using the auto alignment mode. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 175 1: Enables the RX delay alignment counter override with the RXDLY_CFG[14:6] value. RXDDIEN Async RX data delay insertion enable in the deserializer. Set High in RX buffer bypass mode. 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 176 Description RXBUF_EN String Use or bypass the RX elastic buffer. TRUE: Uses the RX elastic buffer (default). FALSE: Bypasses the RX elastic buffer (advanced feature). www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 177 XCLK. Used when bypassing the RX elastic buffer. RXPH_CFG 24-bit Binary Reserved. The recommended value from the 7 Series FPGAs Transceivers Wizard should be used. RXPH_MONITOR_SEL 5-bit Binary Reserved. The recommended value from the 7 Series FPGAs Transceivers Wizard should be used.
  • Page 178 To set up RX buffer bypass in single-lane auto mode, these attributes should be set: • RXSYNC_MULTILANE = 0 • RXSYNC_OVRD = 0 Set the ports as per Figure 4-36. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 179 GTP transceiver reset or rate change. If the received data evaluated at the fabric interface is invalid, the RX phase alignment needs to be repeated while the RX CDR is locked. 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback...
  • Page 180 When the RX elastic buffer is bypassed, the RX phase alignment procedure must be performed after these conditions: • Resetting or powering up the GTP transceiver receiver www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 181 11. Assert RXDLYEN for the master lane. This causes RXPHALIGNDONE to be deasserted. 12. Hold RXDLYEN for the master lane High until the rising edge of RXPHALIGNDONE of the master lane is observed. 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback...
  • Page 182 Slave: These are all the lanes that share the same RXUSRCLK/RXUSRCLK2, which is generated from the RXOUTCLK of the buffer bypass master. Figure 4-40 shows an example of buffer bypass master versus slave lanes. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 183 To set up RX buffer bypass in multi-lane auto mode, the following attributes should be set: • RXSYNC_MULTILANE = 1 • RXSYNC_OVRD = 0 The ports should be set as shown in Figure 4-41. 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 184 RXDLYSRESET UG482_c4_141_020613 Figure 4-41: RX Buffer Bypass—Multi-Lane Auto Mode Port Connection Figure 4-42 shows the required steps to perform auto RX phase and delay alignment. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 185 RXELECIDLE is deasserted on any lane. RX CDR of all lanes needs to be locked before starting the RX alignment procedure. This requirement is to make sure the RX recovered clocks and RXUSRCLK are stable and ready before alignment. 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback...

  • Page 186: Rx Elastic Buffer

    RX Buffer Bypass, page 174). All RX datapaths must use one of these approaches. The costs and benefits of each approach are shown in Table 4-32. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 187 RXREC: Selects the RX recovered clock as the source of XCLK. Used when using the RX elastic buffer. RXUSR: Selects RXUSRCLK as the source of XCLK. Used when bypassing the RX elastic buffer. 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 188 Type Description RX_BUFFER_CFG 6-bit Binary RX elastic buffer configuration. Reserved. The recommended value from the 7 Series FPGAs Transceivers Wizard should be used. RX_DEFER_RESET_BUF_EN String Defer RX elastic buffer reset on comma realignment. The time deferred is controlled by RXBUF_EIDLE_HI_CNT.
  • Page 189 If the data latency through the RX elastic buffer is at or above this threshold, the buffer is considered to be in an overflow condition. Used when RXBUF_THRESH_OVRD = TRUE. Reserved. The recommended value from the 7 Series FPGAs Transceivers Wizard should be used. RXBUF_THRESH_UNDFLW Integer RX elastic buffer underflow threshold specified as number of bytes.

  • Page 190: Rx Clock Correction

    RX elastic buffer is too full and replicating characters when the RX elastic buffer is too empty, the receiver can prevent overflow or underflow. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 191 Elastic Buffer Can Overflow When Read Clock Slower Than Write Clock Remove Special Character to Realign Pointer Difference to Normal Condition UG482_c4_26_071612 Figure 4-44: Clock Correction Conceptual View 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 192 When RX8B10BEN is Low, CBCC_DATA_SOURCE_SEL = DECODED is not supported. CBCC_DATA_SOURCE_SEL = ENCODED, the clock correction sequence matches the raw data from the comma detection and realignment block. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 193 CLK_COR_MAX_LAT, the clock correction circuit removes incoming clock correction sequences to prevent overflow. The 7 Series FPGAs Transceivers Wizard chooses an optimal CLK_COR_MAX_LAT value based on application requirements. The value selected by the Wizard must be followed to maintain optimal performance and must not be overridden.
  • Page 194 Sets the bit width of the RXDATA port. When 8B/10B encoding is enabled, RX_DATA_WIDTH must be set to 20 or 40. Valid settings are 16, 20, 32, and Interface Width Configuration, page 214 for more details. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...

  • Page 195: Enabling Clock Correction

    Similarly, when the number of bytes in the RX elastic buffer exceeds CLK_COR_MAX_LAT, the clock correction circuit deletes CLK_COR_SEQ_LEN bytes from the first clock correction sequence it matches, starting with the first byte of the sequence. The 7 Series FPGAs Transceivers Wizard chooses an optimal setting for CLK_COR_MIN_LAT and CLK_COR_MAX_LAT based on application requirements.

  • Page 196: Setting Clock Correction Sequences

    CLK_COR_SEQ_2_ENABLE. When the enable bit for a sequence is Low, that byte is considered matched no matter what the value is. Figure 4-46 shows the mapping between the clock correction sequences and the clock correction sequence enable bits. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...

  • Page 197: Rx Channel Bonding

    GTP transceiver transmitters used for a bonded channel all transmit a channel bonding character (or a sequence of characters) simultaneously. When the sequence is received, the GTP transceiver receiver can determine the 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback...
  • Page 198 Figure 4-47: Channel Bonding Conceptual View RX channel bonding supports 8B/10B encoded data but does not support these encoded data types: • 64B/66B • 64B/67B • 128B/130B • Scrambled data www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 199 This port cannot be driven High at the same time as RXCHBONDMASTER. RXCHBONDEN RXUSRCLK2 This port enables channel bonding (from the FPGA logic to both the master and slaves). 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 200 When set to DECODED, selects data from the 8B/10B decoder when RX8B10BEN is High. When set to ENCODED, selects data from the comma detection and realignment block. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 201 TXCHARDISPVAL to support PIPE encode and FTS lane deskew. It also works together with TXELECIDLE to match a shorter sequence from reusing prior channel bonding information after the GTP transceiver returns from electrical idle. 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...

  • Page 202: Enabling Channel Bonding

    When GTP transceivers are directly connected, meeting the timing constraints becomes difficult as the transceivers get further apart. The solution to this problem is to connect the transceivers in a www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 203 To set up a daisy chain, the GTP transceivers are first connected using RXCHBONDO and RXCHBONDI to create a path from the RXCHBONDI port of each slave to the RXCHBONDO 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback...
  • Page 204 As with clock correction sequences, channel bonding sequences can have don’t care subsequences. CHAN_BOND_SEQ_1_ENABLE and CHAN_BOND_SEQ_2_ENABLE set these bytes. Figure 4-51 shows the mapping of the enable attributes for the channel bonding subsequences. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...

  • Page 205: Setting The Maximum Skew

    CHAN_BOND_MAX_SKEW is used to set the maximum skew allowed for channel bonding sequences 1 and 2. The maximum skew range is 1 to 14. This range must always be less than 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback...

  • Page 206: Rx Gearbox

    FPGA logic. RXHEADER[2:0] RXUSRCLK2 Header outputs for 64B/66B (1:0) and 64B/67B (2:0). www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 207 The RX gearbox supports 2-byte and 4-byte logic interfaces to the FPGA logic. As shown in Figure 4-53, either mode uses the RXDATA, RXHEADER, RXDATAOUTVALID, and RXHEADEROUTVALID outputs in addition to the RXGEARBOXSLIP input. 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 208 RX gearbox for 64B/66B encoding when using a 2-byte logic interface (RX_DATA_WIDTH = 16 (2-byte)). www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 209 D15 D14 ……………… D15 D14 ………… H1 H0 RXDATA RXHEADER Output of the RXHEADEROUTVALID = 1'b1 RXGearbox RXDATAOUTVALID = 1'b1 UG482_c4_36_111011 Figure 4-54: RX Gearbox Operation 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 210 The RXGEARBOXSLIP input port is used to change the gearbox data alignment so that all possible alignments can be checked. The RXGEARBOXSLIP signal feeds back from the block www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 211 RX gearbox, a block synchronization state machine is required in the FPGA logic. Figure 4-57 shows the operation of a block synchronization state machine. The 7 Series FPGAs Transceivers Wizard has example code for this type of module. X-Ref Target - Figure 4-57 LOCK_INIT block_lock <= false...
  • Page 212 Slip data asserts slip as soon as it sees bad header. alignment RXDATAVALID RXGEARBOXSLIP RXHEADER RXHEADERVALID RXSTARTOFSEQ UG482_c4_40_111011 Figure 4-58: RX Gearbox with Block Synchronization www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...

  • Page 213: Fpga Rx Interface

    Interface Width Configuration The 7 series GTP transceiver contains a 2-byte internal datapath. The FPGA interface width is configurable by setting the RX_DATA_WIDTH attribute. When the 8B/10B decoder is enabled, RX_DATA_WIDTH must be configured to 20 bits or 40 bits, and in this case, the FPGA RX interface only uses the RXDATA port.
  • Page 214 If clock correction is used, RXUSRCLK and RXUSRCLK2 can be sourced by RXOUTCLK or TXOUTCLK. Ports and Attributes Table 4-46 defines the FPGA RX interface ports. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 215 Sets the bit width of the RXDATA port. When 8B/10B encoding is enabled, RX_DATA_WIDTH must be set to 20 or 40. Valid settings are 16, 20, 32, or 40. Interface Width Configuration, page 214 for more details. 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 216 Chapter 4: Receiver www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...

  • Page 217: Chapter 5: Board Design Guidelines

    Board Design Guidelines Overview Topics related to implementing a design on a printed circuit board using the 7 series Artix™-7 FPGA GTP transceivers are presented in this chapter. The GTP transceivers are analog circuits that require special consideration and attention when designing and implementing them on a printed circuit board.
  • Page 218 Figure 5-1: Artix-7 FPGA GTP Power Supply Connections Notes relative to Figure 5-1: Nominal values. Refer to DS181, Artix-7 FPGAs Data Sheet: DC and Switching Characteristics for values and tolerances. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 219 Data In Term. UG482_c5_02_021113 Figure 5-2: 7 Series FPGAs GTP Transceiver Internal Power Supply Connections Termination Resistor Calibration Circuit There is one resistor calibration circuit (RCAL) for each GTP Quad. The MGTRREF pin is used to connect the bias circuit power and the external calibration resistor to the RCAL circuit. The RCAL circuit performs the resistor calibration only during configuration of the FPGA.
  • Page 220 XC7A25T-CSG325 Single XC7A35T-CPG236 Single XC7A35T-CSG325 Single XC7A35T-FGG484 Single XC7A50T-CPG236 Single XC7A50T-CSG325 Single XC7A50T-FGG484 Single XC7A75T-FGG484 Single XC7A75T-FGG676 XC7A100T-FGG484 Single XC7A100T-FGG676 XC7A200T-SBG484 Single XC7A200T-FBG484 Single XC7A200T-FBG676 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 221 MGT supplies. The FGG676 and FBG676 packages have two power planes for each of the MGT supplies. The FFG1156 package also has two power planes for each of the MGT supplies. 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 222 (G10) and (G11) denote package power planes. The GTP Quad power connections are common to all GTP Quads that have the same package power plane. Devices without this notation have only one set of GTP package power planes. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 223 GTP transceivers that are not used. Table 5-6: Unused GTP Quad Column Connections Pin or Pin Pair of the Unused GTP Quad Connection MGTAVCC AVCC MGTAVTT AVTT 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...

  • Page 224: Reference Clock

    This figure is provided to show the contrast to the differential clock input voltage swing calculation shown in Figure 5-5. X-Ref Target - Figure 5-4 MGTREFCLKP Single-ended Voltage MGTREFCLKN UG482_c5_04_080612 Figure 5-4: Single-Ended Clock Input Voltage Swing, Peak-to-Peak www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 225 Characteristics for exact specifications. X-Ref Target - Figure 5-7 MGTREFCLKP Ω To GTP Dedicated 4/5 MGTAVCC Clock REFCLK Ω Routing MGTREFCLKN UG482_c5_07_080612 Figure 5-7: MGTREFCLK Input Buffer Details 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...

  • Page 226: Gtp Reference Clock Checklist

    Internal to Artix-7 FPGA 0.1µF 0.1µF GTP Reference Clock LVDS Oscillator Input Buffer UG482_c5_08_080612 Figure 5-8: Interfacing LVDS Oscillator to Artix-7 FPGA GTP Reference Clock Input www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 227 The GTP reference clock input circuit is powered by MGTAVCC. Excessive noise on this supply will have a negative impact on the performance of any GTP Quad that uses the reference clock from this circuit. 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback...

  • Page 228: Power Supply And Filtering

    Another advantage of the linear regulator is that it usually requires a minimal number of external components to realize a circuit on the printed circuit board. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 229 There is de-coupling capacitance on the die to filter the highest frequency noise components on the power supplies. The source for this very high frequency noise will be the internal on-die circuits. 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 230 The via hole needs to be filled to keep the solder from wicking into the via. See Figure 5-10 an example of placement and routing of the 0.1 µF capacitors. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 231 View From Bottom of PCB 1 mm. Filled Via in Pad 0201 Capacitor UG482_c5_11_072412 Figure 5-11: Placement of 0.1 µF 0201 Capacitor Using Filled Via in Pad Under FPGA 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 232 Cap3 Cap4 Table 5-9: CPG236 Package – 0.1 µF Capacitor Placement Package Pins Value Capacitor MGTAVCC MGTAVTT Cap1 0.1 µF Cap2 Cap3 0.1 µF Cap4 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 233 Table 5-12: FGG676/FBG676 Package – 0.1 µF Capacitor Placement Package Pins Power Supply Capacitor Value Group MGTAVCC MGTAVTT Cap1 Cap2 AA12 AB12 Cap5 Cap6 AD15 AC15 0.1 µF Cap3 Cap4 Cap7 Cap8 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 234 That victim could be a signal or power via for the MGTs. www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...

  • Page 235: Selectio Usage Guidelines

    • Receiver data traces should be provided enough clearance to eliminate crosstalk from adjacent MGTRXP3/MGTRXN3 signals. • If a receiver is not used connect the associated pin pair to ground. • See RX Analog Front End, page 126. 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 236 MGTAVTT. Refer to to identify in which power supply group a specific GTP Quad is located. Information on pin locations for each package can be found i in UG475, 7 Series FPGAs Packaging and Pinout Specifications. • The following set of ceramic filter capacitors for each power supply group are recommended: •...

  • Page 237: Appendix A: Placement Information By Package

    FBG484 Package Placement Diagram, page 244 • SBG484 Package Placement Diagram, page 245 • FBG676 Package Placement Diagram, page 246 • FFG1156 Package Placement Diagram, page 248 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...

  • Page 238: Cpg236 Package Placement Diagram

    GTPE2_ _X0Y0 XC7A15T: MGTPTXP0_216 GTPE2_CHANNEL_X0Y0 MGTPTXN0_216 XC7A25T: CHANNEL GTPE2_ _X0Y0 MGTPRXP0_216 XC7A35T: MGTPRXN0_216 GTPE2_CHANNEL_X0Y0 XC7A50T: GTPE2_CHANNEL_X0Y0 UG482_aA_11_121916 Figure A-1: Placement Diagram for the CPG236 Package www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...

  • Page 239: Csg325 Package Placement Diagram

    XC7A50T: GTPE2_CHANNEL_X0Y1 XC7A12T: GTPE2_CHANNEL_X0Y0 MGTPTXP0_216 XC7A15T: GTPE2_CHANNEL_X0Y0 MGTPTXN0_216 XC7A25T: GTPE2_CHANNEL_X0Y0 MGTPRXP0_216 XC7A35T: MGTPRXN0_216 GTPE2_CHANNEL_X0Y0 XC7A50T: GTPE2_CHANNEL_X0Y0 UG482_aA_13_111016 Figure A-2: Placement Diagram for the CSG325 Package 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...

  • Page 240: Clg485 Package Placement Diagram

    MGTPTXP1_112 XC7Z012S: MGTPTXN1_112 GTPE2_CHANNEL_X0Y1 XC7Z015: MGTPRXP1_112 GTPE2_CHANNEL_X0Y1 MGTPRXN1_112 MGTPTXP0_112 XC7Z012S: MGTPTXN0_112 GTPE2_CHANNEL_X0Y0 XC7Z015: MGTPRXP0_112 GTPE2_CHANNEL_X0Y0 MGTPRXN0_112 UG482_aA_12_121916 Figure A-3: Placement Diagram for the CLG485 Package www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...

  • Page 241: Fgg484 Package Placement Diagram

    XC7A35T:GTPE2_CHANNEL_X0Y1 MGTPTXN1_216 XC7A50T:GTPE2_CHANNEL_X0Y1 XC7A75T:GTPE2_CHANNEL_X0Y5 MGTPRXP1_216 XC7A100T:GTPE2_CHANNEL_X0Y5 MGTPRXN1_216 MGTPTXP0_216 XC7A15T:GTPE2_CHANNEL_X0Y0 XC7A35T:GTPE2_CHANNEL_X0Y0 MGTPTXN0_216 XC7A50T:GTPE2_CHANNEL_X0Y0 XC7A75T:GTPE2_CHANNEL_X0Y4 MGTPRXP0_216 XC7A100T:GTPE2_CHANNEL_X0Y4 MGTPRXN0_216 UG482_aA_01_110514 Figure A-4: Placement Diagram for the FGG484 Package 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...

  • Page 242: Fgg676 Package Placement Diagram

    MGTPTXN1_216 XC7A100T: MGTPRXP1_216 GTPE2_CHANNEL_X0Y5 MGTPRXN1_216 MGTPTXP0_216 XC7A75T: GTPE2_CHANNEL_X0Y4 MGTPTXN0_216 XC7A100T: MGTPRXP0_216 GTPE2_CHANNEL_X0Y4 MGTPRXN0_216 UG482_aA_02_022614 Figure A-5: Placement Diagram for the FGG676 Package (1 of 2) www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 243 AF13 MGTPRXN1_213 AC10 MGTPTXP0_213 XC7A75T: GTPE2_CHANNEL_X0Y0 AD10 MGTPTXN0_213 XC7A100T: AC12 MGTPRXP0_213 GTPE2_CHANNEL_X0Y0 AD12 MGTPRXN0_213 UG482_aA_03_080513 Figure A-6: Placement Diagram for the FGG676 Package (2 of 2) 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...

  • Page 244: Fbg484 Package Placement Diagram

    XC7A200T: GTPE2_COMMON_X0Y1 MGTREFCLK0P_216 MGTREFCLK0N_216 MGTPTXP1_216 MGTPTXN1_216 XC7A200T: GTPE2_CHANNEL_X0Y5 MGTPRXP1_216 MGTPRXN1_216 MGTPTXP0_216 MGTPTXN0_216 XC7A200T: GTPE2_CHANNEL_X0Y4 MGTPRXP0_216 MGTPRXN0_216 UG482_aA_04_021113 Figure A-7: Placement Diagram for the FBG484 Package www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...

  • Page 245: Sbg484 Package Placement Diagram

    XC7A200T: GTPE2_COMMON_X0Y1 MGTREFCLK0P_216 MGTREFCLK0N_216 MGTPTXP1_216 MGTPTXN1_216 XC7A200T: GTPE2_CHANNEL_X0Y5 MGTPRXP1_216 MGTPRXN1_216 MGTPTXP0_216 MGTPTXN0_216 XC7A200T: GTPE2_CHANNEL_X0Y4 MGTPRXP0_216 MGTPRXN0_216 UG482_aA_04_021113 Figure A-8: Placement Diagram for the SBG484 Package 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...

  • Page 246: Fbg676 Package Placement Diagram

    MGTREFCLK0N_216 MGTPTXP1_216 MGTPTXN1_216 XC7A200T: GTPE2_CHANNEL_X0Y5 MGTPRXP1_216 MGTPRXN1_216 MGTPTXP0_216 MGTPTXN0_216 XC7A200T: GTPE2_CHANNEL_X0Y4 MGTPRXP0_216 MGTPRXN0_216 UG482_aA_05_021113 Figure A-9: Placement Diagram for the FBG676 Package (1 of 2) www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 247 AE13 MGTPRXP1_213 AF13 MGTPRXN1_213 AC10 MGTPTXP0_213 AD10 MGTPTXN0_213 XC7A200T: GTPE2_CHANNEL_X0Y0 AC12 MGTPRXP0_213 AD12 MGTPRXN0_213 UG482_aA_06_021113 Figure A-10: Placement Diagram for the FBG676 Package (2 of 2) 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...

  • Page 248: Ffg1156 Package Placement Diagram

    MGTREFCLK0N_216 MGTPTXP1_216 MGTPTXN1_216 XC7A200T: GTPE2_CHANNEL_X0Y5 MGTPRXP1_216 MGTPRXN1_216 MGTPTXP0_216 MGTPTXN0_216 XC7A200T: GTPE2_CHANNEL_X0Y4 MGTPRXP0_216 MGTPRXN0_216 UG482_aA_07_021113 Figure A-11: Placement Diagram for the FFG1156 Package (1 of 4) www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 249 MGTREFCLK0N_116 MGTPTXP1_116 MGTPTXN1_116 XC7A200T: GTPE2_CHANNEL_X1Y5 MGTPRXP1_116 MGTPRXN1_116 MGTPTXP0_116 MGTPTXN0_116 XC7A200T: GTPE2_CHANNEL_X1Y4 MGTPRXP0_116 MGTPRXN0_116 UG482_aA_08_021113 Figure A-12: Placement Diagram for the FFG1156 Package (2 of 4) 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 250 AJ19 MGTPRXP1_213 AK19 MGTPRXN1_213 AN19 MGTPTXP0_213 AP19 MGTPTXN0_213 XC7A200T: GTPE2_CHANNEL_X0Y0 AL18 MGTPRXP0_213 AM18 MGTPRXN0_213 UG482_aA_09_021113 Figure A-13: Placement Diagram for the FFG1156 Package (3 of 4) www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 251 AL16 MGTPRXP1_113 AM16 MGTPRXN1_113 AN17 MGTPTXP0_113 AP17 MGTPTXN0_113 XC7A200T: GTPE2_CHANNEL_X1Y0 AJ17 MGTPRXP0_113 AK17 MGTPRXN0_113 UG482_aA_10_021113 Figure A-14: Placement Diagram for the FFG1156 Package (4 of 4) 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 252 Appendix A: Placement Information by Package www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 253 _116, XC7A200T _216 _216 MGT_BANK MGT_BANK _216 _213, MGT_BANK _216 Table B-2: Zynq-7000 Device/Package Combinations and GTP Transceiver Banks Package CLG485 XC7Z012S MGT_BANK_112 XC7Z015 MGT_BANK_112 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 254 Appendix B: Placement Information by Device www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 255 100011 1011 100011 0100 D18.0 000 10010 010011 1011 010011 0100 D19.0 000 10011 110010 1011 110010 0100 D20.0 000 10100 001011 1011 001011 0100 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 256 100011 1001 100011 1001 D18.1 001 10010 010011 1001 010011 1001 D19.1 001 10011 110010 1001 110010 1001 D20.1 001 10100 001011 1001 001011 1001 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 257 100011 0101 100011 0101 D18.2 010 10010 010011 0101 010011 0101 D19.2 010 10011 110010 0101 110010 0101 D20.2 010 10100 001011 0101 001011 0101 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 258 100011 1100 100011 0011 D18.3 011 10010 010011 1100 010011 0011 D19.3 011 10011 110010 1100 110010 0011 D20.3 011 10100 001011 1100 001011 0011 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 259 100011 1101 100011 0010 D18.4 100 10010 010011 1101 010011 0010 D19.4 100 10011 110010 1101 110010 0010 D20.4 100 10100 001011 1101 001011 0010 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 260 100011 1010 100011 1010 D18.5 101 10010 010011 1010 010011 1010 D19.5 101 10011 110010 1010 110010 1010 D20.5 101 10100 001011 1010 001011 1010 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 261 100011 0110 100011 0110 D18.6 110 10010 010011 0110 010011 0110 D19.6 110 10011 110010 0110 110010 0110 D20.6 110 10100 001011 0110 001011 0110 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 262 100011 0111 100011 0001 D18.7 111 10010 010011 0111 010011 0001 D19.7 111 10011 110010 1110 110010 0001 D20.7 111 10100 001011 0111 001011 0001 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 263 110110 1000 001001 0111 K29.7 111 11101 101110 1000 010001 0111 K30.7 111 11110 011110 1000 100001 0111 Notes: 1. Used for testing and characterization only. 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 264 Appendix C: 8B/10B Valid Characters www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 265 The reserved bits should NOT be modified. Attributes that are not described explicitly are set automatically by the 7 Series FPGAs Transceivers Wizard. These attributes must be left at their defaults, except for use cases that explicitly request different values.
  • Page 266 0-255 0029 PLL1_LOCK_CFG 0-511 0-511 002A 13:9 PLL1_REFCLK_DIV 002B PLL1_FBDIV_45 002B PLL1_FBDIV 002B 15:0 PLL1_CFG 15:0 0-65535 0-65535 002C 10:0 PLL1_CFG 26:16 0-2047 0-2047 002D www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 267 The reserved bits should NOT be modified. Attributes that are not described explicitly are set automatically by the 7 Series FPGAs Transceivers Wizard. These attributes must be left at their defaults, except for use cases that explicitly request different values.
  • Page 268 Attribute DRP Bits Attribute Name Address Bits Encoding Encoding 0011 10:6 RX_CLK25_DIV (Cont’d) RX_CM_SEL 0011 RXPRBS_ERR_LOOPBACK 0011 15:12 SATA_BURST_SEQ_LEN 0-15 0-15 0012 11:10 OUTREFCLK_SEL_INV 0012 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 269 Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont’d) Attribute Attribute DRP Bits Attribute Name Address Bits Encoding Encoding SATA_BURST_VAL 0012 RXOOB_CFG 0-127 0-127 0012 14:9 SAS_MIN_COM 0013 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 270 DRP Address Map of the GTP Transceiver Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont’d) Attribute Attribute DRP Bits Attribute Name Address Bits Encoding Encoding 0013 14:9 SAS_MIN_COM (Cont’d) www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 271 Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont’d) Attribute Attribute DRP Bits Attribute Name Address Bits Encoding Encoding SATA_MIN_BURST 0013 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 272 Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont’d) Attribute Attribute DRP Bits Attribute Name Address Bits Encoding Encoding 0013 SATA_MIN_BURST (Cont’d) SATA_EIDLE_VAL 0013 11:6 SATA_MIN_WAKE 0014 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 273 Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont’d) Attribute Attribute DRP Bits Attribute Name Address Bits Encoding Encoding 0014 11:6 SATA_MIN_WAKE (Cont’d) 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 274 DRP Address Map of the GTP Transceiver Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont’d) Attribute Attribute DRP Bits Attribute Name Address Bits Encoding Encoding 0014 11:6 SATA_MIN_WAKE (Cont’d) SATA_MIN_INIT 0014 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 275 Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont’d) Attribute Attribute DRP Bits Attribute Name Address Bits Encoding Encoding 0014 SATA_MIN_INIT (Cont’d) 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 276 DRP Address Map of the GTP Transceiver Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont’d) Attribute Attribute DRP Bits Attribute Name Address Bits Encoding Encoding 0014 SATA_MIN_INIT (Cont’d) 12:6 SAS_MAX_COM 0015 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 277 Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont’d) Attribute Attribute DRP Bits Attribute Name Address Bits Encoding Encoding 0015 12:6 SAS_MAX_COM (Cont’d) 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 278 DRP Address Map of the GTP Transceiver Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont’d) Attribute Attribute DRP Bits Attribute Name Address Bits Encoding Encoding 0015 12:6 SAS_MAX_COM (Cont’d) www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 279 Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont’d) Attribute Attribute DRP Bits Attribute Name Address Bits Encoding Encoding 0015 12:6 SAS_MAX_COM (Cont’d) 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 280 DRP Address Map of the GTP Transceiver Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont’d) Attribute Attribute DRP Bits Attribute Name Address Bits Encoding Encoding 0015 12:6 SAS_MAX_COM (Cont’d) SATA_MAX_BURST 0015 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 281 Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont’d) Attribute Attribute DRP Bits Attribute Name Address Bits Encoding Encoding 0015 SATA_MAX_BURST (Cont’d) 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 282 DRP Address Map of the GTP Transceiver Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont’d) Attribute Attribute DRP Bits Attribute Name Address Bits Encoding Encoding 0015 SATA_MAX_BURST (Cont’d) 11:6 SATA_MAX_WAKE 0016 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 283 Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont’d) Attribute Attribute DRP Bits Attribute Name Address Bits Encoding Encoding 0016 11:6 SATA_MAX_WAKE (Cont’d) 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 284 DRP Address Map of the GTP Transceiver Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont’d) Attribute Attribute DRP Bits Attribute Name Address Bits Encoding Encoding 0016 11:6 SATA_MAX_WAKE (Cont’d) SATA_MAX_INIT 0016 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 285 Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont’d) Attribute Attribute DRP Bits Attribute Name Address Bits Encoding Encoding 0016 SATA_MAX_INIT (Cont’d) 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 286 Encoding 0016 SATA_MAX_INIT (Cont’d) 15:11 RXOSCALRESET_TIMEOUT 0-31 0-31 0017 10:6 RXOSCALRESET_TIME 0-31 0-31 0017 TRANS_TIME_RATE 0-255 0-255 0018 PMA_LOOPBACK_CFG 0019 TX_PREDRIVER_MODE 0019 11:9 TX_EIDLE_DEASSERT_DELAY 0019 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 287 0031 15:0 ES_QUAL_MASK 31:16 0-65535 0-65535 0032 15:0 ES_QUAL_MASK 47:32 0-65535 0-65535 0033 15:0 ES_QUAL_MASK 63:48 0-65535 0-65535 0034 15:0 ES_QUAL_MASK 79:64 0-65535 0-65535 0035 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 288 0-63 0-63 003D ALIGN_COMMA_ENABLE 0-1023 0-1023 003E ALIGN_MCOMMA_VALUE 0-1023 0-1023 003F AUTO 15:14 RXSLIDE_MODE 0040 ALIGN_PCOMMA_VALUE 0-1023 0-1023 0040 14:13 ALIGN_COMMA_WORD 0041 12:8 RX_SIG_VALID_DLY 0041 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 289 Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont’d) Attribute Attribute DRP Bits Attribute Name Address Bits Encoding Encoding 0041 12:8 RX_SIG_VALID_DLY (Cont’d) FALSE ALIGN_PCOMMA_DET 0041 TRUE 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 290 SHOW_REALIGN_COMMA 0041 TRUE FALSE ALIGN_COMMA_DOUBLE 0041 TRUE RXSLIDE_AUTO_WAIT 0041 FALSE CLK_CORRECT_USE 0044 TRUE 13:10 CLK_COR_SEQ_1_ENABLE 0-15 0-15 0044 CLK_COR_SEQ_1_1 0-1023 0-1023 0044 15:10 CLK_COR_MAX_LAT 0045 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 291 Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont’d) Attribute Attribute DRP Bits Attribute Name Address Bits Encoding Encoding 0045 15:10 CLK_COR_MAX_LAT (Cont’d) 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 292 Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont’d) Attribute Attribute DRP Bits Attribute Name Address Bits Encoding Encoding 0045 15:10 CLK_COR_MAX_LAT (Cont’d) CLK_COR_SEQ_1_2 0-1023 0-1023 0045 15:10 CLK_COR_MIN_LAT 0046 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 293 Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont’d) Attribute Attribute DRP Bits Attribute Name Address Bits Encoding Encoding 0046 15:10 CLK_COR_MIN_LAT (Cont’d) 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 294 Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont’d) Attribute Attribute DRP Bits Attribute Name Address Bits Encoding Encoding 0046 15:10 CLK_COR_MIN_LAT (Cont’d) CLK_COR_SEQ_1_3 0-1023 0-1023 0046 14:10 CLK_COR_REPEAT_WAIT 0047 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 295 0-15 0048 CLK_COR_SEQ_2_1 0-1023 0-1023 0048 FALSE CLK_COR_KEEP_IDLE 0049 TRUE FALSE CLK_COR_PRECEDENCE 0049 TRUE 11:10 CLK_COR_SEQ_LEN 0049 CLK_COR_SEQ_2_2 0-1023 0-1023 0049 CLK_COR_SEQ_2_3 0-1023 0-1023 004A 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 296 0051 FALSE FTS_LANE_DESKEW_EN 0051 TRUE CHAN_BOND_SEQ_2_2 0-1023 0-1023 0051 15:12 FTS_DESKEW_SEQ_ENABLE 0-15 0-15 0052 ENCODED CBCC_DATA_SOURCE_SEL 0052 DECODED CHAN_BOND_SEQ_2_3 0-1023 0-1023 0052 15:12 CHAN_BOND_MAX_SKEW 0053 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 297 005E VCO_750MHZ 15:0 TXPHDLY_CFG 15:0 0-65535 0-65535 0060 TXPHDLY_CFG 23:16 0-255 0-255 0061 15:0 TXDLY_CFG 15:0 0-65535 0-65535 0062 15:0 TXDLY_TAP_CFG 15:0 0-65535 0-65535 0063 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 298 0065 15:0 RX_BIAS_CFG 15:0 0-65535 0-65535 0066 RXOOB_CLK_CFG 0068 FABRIC TX_CLKMUX_EN 0068 RX_CLKMUX_EN 0068 14:0 TERM_RCAL_CFG 14:0 0-32767 0-32767 0069 15:13 TERM_RCAL_OVRD 006A TX_CLK25_DIV 006A www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 299 0-127 0078 14:8 TX_MARGIN_LOW_4 0-127 0-127 0079 TX_MARGIN_LOW_3 0-127 0-127 0079 13:8 TX_DEEMPH1 0-63 0-63 007A TX_DEEMPH0 0-63 0-63 007A 10:8 TX_RXDETECT_REF 007C TX_MAINCURSOR_SEL 007C 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 300 0-2047 0-2047 008B CFOK_CFG3 0-127 0-127 008C 15:13 RXPI_CFG0 008D RXLPM_CM_CFG 008D 11:10 CFOK_CFG5 008D RXLPM_LF_CFG2 0-31 0-31 008D RXLPM_HF_CFG2 0-31 0-31 008D RXLPM_IPCM_CFG 008E www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 301 PMA_RSV 15:0 0-65535 0-65535 0099 15:0 PMA_RSV 31:16 0-65535 0-65535 009A RX_BUFFER_CFG 0-63 0-63 009B FALSE RXBUF_THRESH_OVRD 009C TRUE FALSE RXBUF_RESET_ON_EIDLE 009C TRUE RXBUF_THRESH_UNDFLW 009C 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 302 DRP Address Map of the GTP Transceiver Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont’d) Attribute Attribute DRP Bits Attribute Name Address Bits Encoding Encoding 009C RXBUF_THRESH_UNDFLW (Cont’d) www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 303 DRP Bits Attribute Name Address Bits Encoding Encoding 009C RXBUF_THRESH_UNDFLW (Cont’d) 15:12 RXBUF_EIDLE_HI_CNT 0-15 0-15 009D 11:8 RXBUF_EIDLE_LO_CNT 0-15 0-15 009D FULL RXBUF_ADDR_MODE 009D FAST 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 304 DRP Address Map of the GTP Transceiver Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont’d) Attribute Attribute DRP Bits Attribute Name Address Bits Encoding Encoding RXBUF_THRESH_OVFLW 009D www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 305 Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont’d) Attribute Attribute DRP Bits Attribute Name Address Bits Encoding Encoding 009D RXBUF_THRESH_OVFLW (Cont’d) 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com Send Feedback UG482 (v1.9) December 19, 2016...
  • Page 306 31:16 0-65535 0-65535 00A9 15:0 RXCDR_CFG 47:32 0-65535 0-65535 00AA 15:0 RXCDR_CFG 63:48 0-65535 0-65535 00AB 15:0 RXCDR_CFG 79:64 0-65535 0-65535 00AC RXCDR_CFG 82:80 00AD www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide Send Feedback UG482 (v1.9) December 19, 2016...

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