Transmitter; Synchronizing The Pma/Pcs Clocks In Low-Latency Modes - Xilinx Virtex-4 RocketIO User Manual

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Transmitter

Table 8-5: TX Low-Latency Ports
Notes:
1. 64B/66B encoding/decoding is not supported.
2. Refer to
Table 8-6: TX Low-Latency Attributes
Notes:
1. 64B/66B encoding/decoding is not supported.
2. PCS TXCLK is the TX PCS parallel clock, the TX buffer read clock. Refer to

Synchronizing the PMA/PCS Clocks in Low-Latency Modes

The TXSYNC and RXSYNC ports are used to enable low-latency modes by activating the
phase-alignment functions of the PMA. Asserting TXSYNC or RXSYNC causes the
TX PMA or RX PMA to synchronize the PCS and PMA clocks. This operation should be
performed only after the PLL is locked. See
establishing lock.
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
PORTS
TXENC8B10BUSE
TXENC64B66BUSE
TXSCRAM64B66BUSE
TXGEARBOX64B66BUSE
TXSYNC
Figure 8-2.
ATTRIBUTES
TX_BUFFER_USE
TXDATA_SEL
TXCLK0_FORCE_PMACLK
TX_CLOCK_DIVIDER
TXPHASESEL
and Figure 2-8, page 75 for more details.
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Synchronizing the PMA/PCS Clocks in Low-Latency Modes
(1)
Determines Encoding bypass mode in conjunction with
TXENC64B66BUSE
Determines Encoding bypass mode in conjunction with
(2)
TXENC8B10BUSE
Determines Global bypass mode in conjunction with
TXDATA_SEL and TXGEARBOX64B66BUSE
Determines Global bypass mode in conjunction with
TXDATA_SEL and TXSCRAM64B66BUSE
Enables synchronization of PMA (PMA TXCLK0) and PCS
(PCS TXCLK or GREFCLK) clocks in TX low-latency buffer
bypass mode
(1)
Determines buffer bypass mode
Determines Global bypass mode in conjunction with
TXSCRAM64B66BUSE and TXGEARBOX64B66BUSE
Determines if PMA TXCLK0 or TXUSRCLK sources the
(2)
PCS TXCLK
Determines the clock source for the TXUSRCLK domain.
Combination of TX_CLOCK_DIVIDER and
TXCLK0_FORCE_PMACLK determines the source for the
PCS TXCLK domain
Determines if PCS TXCLK or GREFCLK is used as
synchronization source
"Resets" in Chapter 2
DESCRIPTION
(2)
(2)
(2)
DESCRIPTION
"Attributes" in Chapter 1
for more details on
197