Receiver Lock Control; Receive Equalization - Xilinx Virtex-4 RocketIO User Manual

R
at 1/32
transitions must be present in the data stream for CDR to work properly. The CDR circuit
is guaranteed to work with 8B/10B encoding. Further, CDR requires about 5,000
transitions upon power-up to guarantee locking to the incoming data rate.
Another feature of CDR is its ability to accept an external precision clock, REFCLK, which
acts either to clock incoming data or to assist in synchronizing the derived
RXRECCLK1/RXRECCLK2.

Receiver Lock Control

During normal operation, the receiver PLL automatically locks to incoming data (when
present) or to the local reference clock (when data is not present). This is the default
configuration. This function can be overridden via the RXDIGRX attribute, as defined in
Table
Table 4-3: RXDIGRX Definition
When receive PLL lock is forced to the local reference, phase information from the
incoming data stream is ignored. Data continues to be sampled, but using the local
reference clock rather than a recovered clock.

Receive Equalization

In addition to transmit emphasis, the MGT provides a programmable receive equalization
feature to further compensate the effects of channel attenuation at high frequencies.
Copper traces on printed circuit boards, including backplanes, have low-pass filter
characteristics. The impedance mismatch boundaries can also cause signal degradation.
The MGT has an equalizer in the receiver which can essentially null the lossy attenuation
effects of the PCB at GHz frequencies.
The receiver equalization circuit is comprised of three concatenated gain stages. Each stage
is a peaking equalizer with a different center frequency and programmable gain. This
allows varying amounts of gain to be applied depending on the overall frequency response
of the channel loss. Channel loss is defined as the summation of all losses through the PCB
traces, vias, connectors, and cables present in the physical link.
Ideally, the overall frequency response of the three gain stages should be the inverse of the
overall channel loss response. Fine shaping of the gain response is possible by varying the
gain for each stage and, hence, the gain at each of the three center frequencies.
The attribute RXAFEEQ[2:0] controls the gain settings for the receiver equalizer and can be
adjusted by the Dynamic Reconfiguration Port.
Figure 4-7
From the graph
RXAFEEQ setting. Each curve shows the combined gain response of all three equalizer
stages expressed in dB. Using one of the four settings here provides sufficient receiver
equalization flexibility for most applications. The choice of RXAFEEQ setting depends on
the amount of high-frequency loss in the transmission media. Links with more
transmission loss should use the higher gain settings.
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
nd th
and 1/40 the incoming data rate depending on mode. A sufficient number of
4-3.
RXDIGRX
0
1
shows the AC response of the 3-stage continuous-time linear equalizer.
(Figure 4-8), the four response curves correspond to their respective
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Differential Receiver
Description
Automatic (Default)
Lock to local reference
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