Figure 12-1: Differential Via Dimensions; Channel Budgeting Considerations - Xilinx Virtex-4 RocketIO User Manual

Chapter 12: Guidelines and Examples
microstrip, the via stub can be eliminated. Routing from the top microstrip to the bottom-
most stripline layer results in a negligible via stub. If the lowest layers are not available for
high-speed striplines, other striplines can be used. However, long via stubs might need to
be removed by back-drilling the vias.
Use of minimum spacing and clearance design rules is to be avoided, such as 5 mil pad
clearances. These clearances can be detrimental to performance even at lower multi-gigabit
rates due to the excess capacitance from the tight spacing.
Most transitions shown in this document have 40 fF to 200 fF of excess capacitance. One
exception is a press-fit connector with the PCB pin array having about 500 fF to 800 fF of
excess capacitance using these guidelines, with a via stub less than 10 mils. With smaller
antipads or longer via stubs, the excess capacitance is much greater. Because the Virtex®-4
RocketIO™ transceivers have a die capacitance of 500 fF to 600 fF, most transitions can be
designed to have a very small impact on performance up to speeds beyond 10 Gb/s.

Channel Budgeting Considerations

It can be difficult to select components and board materials for the target data rate. To
further complicate this task, there are many transitions within the channel which can affect
performance. To simplify the channel analysis, an initial loss budget assessment should be
done. Such analyses are presented in examples below. The intent of these exercises is to
focus on the effect that transitions have on the channel. To get a better understanding
regarding the impact of transitions, the differential via whose dimensions are shown in
Figure 12-1
Next, in
the return loss (RL) at 1 GHz for a variety of differential vias with many differing
dimensions. All differential vias are through vias, meaning they extend from the top to the
bottom layers. Therefore, the board thicknesses of 200, 125, and 50 mils are the actual via
lengths. For each board thickness, there are two via diameters to approximately represent
8:1 and 10:1 aspect ratios. Via diameters are in drilled dimension, not finished hole sizes.
There are two via pitches chosen to explore performance versus density trade-offs. All vias
assume a top microstrip entry, and there are cases for:
258
is revisited.
Antipad Width
Drill
Diameter
Pitch

Figure 12-1: Differential Via Dimensions

Table 12-1, page 259 the vias are modeled with a 3-D full-wave solver to calculate
a) a bottom microstrip exit, i.e. no via stub
b) a stripline exit about two-thirds along the via length (a short stub)
c) a stripline exit about one-third along the via length ( a long stub)
www.xilinx.com
Annular Ring
Pitch Pitch
UG076_ch12_02_051006
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
R