Internal Bus Width Configuration - Xilinx Virtex-4 RocketIO User Manual

Chapter 3: PCS Digital Design Considerations
Table 3-1: Selecting the External Configuration

Internal Bus Width Configuration

By using the signals TXINTDATAWIDTH[1:0] and RXINTDATAWIDTH[1:0], the internal
bus width can be designated. This is usually determined by the encoding scheme
implemented. For SONET applications, the internal bus widths should be set to 32 bits. For
8B/10B and other encoding schemes that use alignment on 10-, 20-, or 40-bit boundaries,
the 40-bit internal bus should be used.
Table 3-2
Table 3-2: Selecting the Internal Configuration
Note:
The digital receiver must also have the same data bus width controlled with RXBY_32.
104
RXDATAWIDTH/TXDATAWIDTH
2'b00
2'b01
2'b10
2'b11
shows the available internal bus width settings.
RXINTDATAWIDTH/TXINTDATAWIDTH
2'b10
2'b11
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Data Width
8/10 bit (1 byte)
16/20 bit (2 byte)
32/40 bit (4 byte)
64/80 bit (8 byte)
Internal Data Width
32 bit
40 bit
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
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